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This example streams input from a ADC source to a DAC. An analog signal is acquired block-by-block into SDRAM from the ADC (an AD9244 in this example). The frames are then output with a one-frame delay to the DAC (an AD9744 in this example). In this example, no processing is done on the frames. They are passed unaltered.
標簽： block-by-block acquired example streams
上傳時間： 2015-12-29
上傳用戶：bjgaofei
The IEEE Multipath Channel block simulates an indoor UWB channel as described in "A Channel Model for Ultrawideband Indoor Communications" by J.R. Foerster, M. Pendergrass and A.F. Molisch, November 2003, and attempts to incorporate the processes used in their MATLAB scripts.
標簽： Channel Multipath simulates described
上傳時間： 2015-05-08
上傳用戶：水中浮云
This program simulates plant identification using frequency block least mean square (FBLMS) alogrithm reference: 《LMS算法的頻域快速實現》 LMS is modified by XXX in XXX place, see details in XXX relevant document
標簽： identification frequency simulates alogrith
上傳時間： 2016-02-29
上傳用戶：kytqcool
SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
標簽： high-level following reference diagram
上傳時間： 2013-12-15
上傳用戶：Miyuki
altera fpga 基于vhdl,實現vga的同步block.
上傳時間： 2013-08-26
上傳用戶：hn891122
Protel 自定義Title Block方法
上傳時間： 2014-12-24
上傳用戶：yl1140vista
UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI Express® 用戶指南
標簽： LogiCORE Endpoint Block 341
上傳時間： 2013-10-11
上傳用戶：woshinimiaoye
7.4 基于IP CORE的BLOCK RAM設計修改稿。
上傳時間： 2013-11-07
上傳用戶：sammi
Protel 自定義Title Block方法
上傳時間： 2015-01-01
上傳用戶：黃華強
UG341 - LogiCORE™ Endpoint Block Plus v1.6 for PCI Express® 用戶指南
標簽： LogiCORE Endpoint Block 341
上傳時間： 2013-10-17
上傳用戶：jeffery
