本資料是關(guān)于基于Quartus II FPGA/cPLD數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例（VHDL源代碼文件），需要的可以自己下載。
標(biāo)簽： Quartus FPGA cPLD VHDL
上傳時(shí)間： 2013-11-12
上傳用戶：VRMMO
FPGA-cPLD芯片設(shè)置方法
上傳時(shí)間： 2015-01-01
上傳用戶：luopoguixiong
FPGA與cPLD區(qū)別
上傳時(shí)間： 2013-10-25
上傳用戶：qw12
cPLD最小系統(tǒng)設(shè)計(jì)
標(biāo)簽： cPLD 最小系統(tǒng) 原理圖
上傳時(shí)間： 2013-12-23
上傳用戶：410805624
cPLD開(kāi)發(fā)套件光盤(pán)說(shuō)明
標(biāo)簽： cPLD 開(kāi)發(fā)套件 光盤(pán)
上傳時(shí)間： 2013-10-24
上傳用戶：hfmm633
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the cPLD softwareimplementation (cPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize cPLD utilization.
上傳時(shí)間： 2014-01-11
上傳用戶：a471778
This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (cPLDs). Specifically included are those design practices that translate soundlyto cPLDs, permitting designers to use the best features of this powerful language to extractoptimum performance for cPLD designs.
上傳時(shí)間： 2013-11-21
上傳用戶：gtf1207
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II cPLD device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽： CoolRunner-II XAPP cPLD 380
上傳時(shí)間： 2013-10-26
上傳用戶：kiklkook
The CoolRunner-II cPLD is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional cPLD architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上傳時(shí)間： 2013-11-03
上傳用戶：1037540470
This application note shows how a Xilinx CoolRunnerTM-II cPLD can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining cPLD resources
標(biāo)簽： CoolRunner-II Xilinx XAPP cPLD
上傳時(shí)間： 2013-12-16
上傳用戶：qwer0574
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