Abstract: What can be simpler than designing with CMOS and BiCMOS? These technologies are very easy to use butthey still require careful design. This tutorial discusses the odd case of circuits that seem to work but exhibit somepeculiar behaviors—including burning the designer's fingers!
上傳時(shí)間： 2013-11-03
上傳用戶：dick_sh
Sensors for pressure, load, temperature, acceleration andmany other physical quantities often take the form of aWheatstone bridge. These sensors can be extremely linearand stable over time and temperature. However, mostthings in nature are only linear if you don’t bend them toomuch. In the case of a load cell, Hooke’s law states that thestrain in a material is proportional to the applied stress—as long as the stress is nowhere near the material’s yieldpoint (the “point of no return” where the material ispermanently deformed).
標(biāo)簽： Delta Sigma ADC 測(cè)量技術(shù)
上傳時(shí)間： 2013-11-13
上傳用戶：墻角有棵樹(shù)
Differential Nonlinearity: Ideally, any two adjacent digitalcodes correspond to output analog voltages that are exactlyone LSB apart. Differential non-linearity is a measure of theworst case deviation from the ideal 1 LSB step. For example,a DAC with a 1.5 LSB output change for a 1 LSB digital codechange exhibits 1⁄2 LSB differential non-linearity. Differentialnon-linearity may be expressed in fractional bits or as a percentageof full scale. A differential non-linearity greater than1 LSB will lead to a non-monotonic transfer function in aDAC.Gain Error (Full Scale Error): The difference between theoutput voltage (or current) with full scale input code and theideal voltage (or current) that should exist with a full scale inputcode.Gain Temperature Coefficient (Full Scale TemperatureCoefficient): Change in gain error divided by change in temperature.Usually expressed in parts per million per degreeCelsius (ppm/°C).Integral Nonlinearity (Linearity Error): Worst case deviationfrom the line between the endpoints (zero and full scale).Can be expressed as a percentage of full scale or in fractionof an LSB.LSB (Lease-Significant Bit): In a binary coded system thisis the bit that carries the smallest value or weight. Its value isthe full scale voltage (or current) divided by 2n, where n is theresolution of the converter.Monotonicity: A monotonic function has a slope whose signdoes not change. A monotonic DAC has an output thatchanges in the same direction (or remains constant) for eachincrease in the input code. the converse is true for decreasing codes.
標(biāo)簽： Converters Defini DAC
上傳時(shí)間： 2013-10-30
上傳用戶：stvnash
Calculation of the Differential Impedance of Tracks on FR4 substrates There is a discrepancy between calculated and measured values of impedance for differential transmission lineson FR4. This is especially noticeable in the case of surface microstrip configurations. The anomaly is shown tobe due to the nature of the substrate material. This needs to be considered as a layered structure of epoxy resinand glass fibre. Calculations, using Boundary Element field methods, show that the distribution of the electricfield within this layered structure determines the apparent dielectric constant and therefore affects theimpedance. Thus FR4 cannot be considered to be uniform dielectric when calculating differential impedance.
上傳時(shí)間： 2014-12-24
上傳用戶：DE2542
交流瓦特/瓦特小時(shí)，乏爾/乏爾小時(shí)轉(zhuǎn)換器 特點(diǎn)： 精確度0.25%滿刻度 多種輸入,輸出選擇 輸入與輸出絕緣耐壓2仟伏特/1分鐘 沖擊電壓測(cè)試5仟伏特(1.2x50us) 突波電壓測(cè)試2.5仟伏特(0.25ms/1MHz) (IEC255-4) 尺寸小，穩(wěn)定性高 主要規(guī)格： 精確度: 0.25% F.S. (23 ±5℃) 輸入負(fù)載: <0.2VA (Voltage) <0.2VA (Current) 最大過(guò)載能力: Current related input:3 x rated continuous 10 x rated 30 sec. ,25 x rated 3sec. 50 x rated 1sec. Voltage related input:maximum 2 x rated continuous 輸出反應(yīng)速度: < 250ms(0~90%) 輸出負(fù)載能力: < 10mA for voltage mode < 10V for current mode 輸出之漣波 : < 0.1% F.S. 脈波輸出型態(tài): Photocouple of open collector (max.30V/40mA) 歸零調(diào)整范圍: 0~±5% F.S. 最大值調(diào)整范圍: 0~±10% F.S. 溫度系數(shù): 100ppm/℃ (0~50℃) 隔離特性: Input/Output/Power/case 絕緣阻抗: >100Mohm with 500V DC 絕緣耐壓能力: 2KVac/1 min. (input/output/power/case) 突波測(cè)試: ANSI C37.90a/1974,DIN-IEC 255-4 impulse voltage 5KV(1.2x50us) 使用環(huán)境條件: -20~60℃(20 to 90% RH non-condensed) 存放環(huán)境條件: -30~70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
標(biāo)簽： 瓦特 交流 轉(zhuǎn)換器
上傳時(shí)間： 2013-11-11
上傳用戶：wettetw
Abstract: Rail splitting is creating an artificial virtual ground as a reference voltage. It is used to set the signalto match the op amp's "sweet spot." An op amp has the most linear- and distortion-free qualities at that sweetspot. Typically, the sweet spot occurs near the center between the single power rail and ground. In the case ofa number of signals, the virtual ground can control channel DC errors when multiplexing or switching thesignals.
標(biāo)簽： 電源調(diào)整 虛擬地
上傳時(shí)間： 2013-10-23
上傳用戶：wushengwu
The latest generation of Texas Instruments (TI) boardmountedpower modules utilizes a pin interconnect technologythat improves surface-mount manufacturability.These modules are produced as a double-sided surfacemount(DSSMT) subassembly, yielding a case-less constructionwith subcomponents located on both sides of theprinted circuit board (PCB). Products produced in theDSSMT outline use the latest high-efficiency topologiesand magnetic-component packaging. This providescustomers with a high-efficiency, ready-to-use switchingpower module in a compact, space-saving package. Bothnonisolated point-of-load (POL) switching regulators andthe isolated dc/dc converter modules are being producedin the DSSMT outline.TI’s plug-in power product line offers power modules inboth through-hole and surface-mount packages. The surfacemountmodules produced in the DSSMT outline use asolid copper interconnect with an integral solder ball fortheir
上傳時(shí)間： 2013-10-10
上傳用戶：1184599859
附件為：LCD12864顯示漢字和數(shù)字的程序與電路 /* 自定義延時(shí)子函數(shù) */ void delayms(uchar z) { int x,y; for(x=z;x>0;x--) for(y=110;y>0;y--); } /* 判斷LCD忙信號(hào)狀態(tài) */ void buys() { int dat; RW=1; RS=0; do { P0=0x00; E=1; dat=P0; E=0; dat=0x80 & dat; } while(!(dat==0x00)); } /* LCD寫指令函數(shù) */ void w_com(uchar com) { //buys(); RW=0; RS=0; E=1; P0=com; E=0; } /* LCD寫數(shù)據(jù)函數(shù) */ void w_date(uchar date) { //buys(); RW=0; RS=1; E=1; P0=date; E=0; } /* LCD選屏函數(shù) */ void select_screen(uchar screen) { switch(screen) { case 0: //選擇全屏 CS1=0; CS2=0; break; case 1: //選擇左屏 CS1=0; CS2=1; break; case 2: //選擇右屏 CS1=1; CS2=0; break; /* case 3: //選擇右屏 CS1=1; CS2=1; break; */ } } /* LCDx向上滾屏顯示 */ void lcd_rol() { int x; for(x=0;x<64;x++) { select_screen(0); w_com(0xc0+x); delayms(500); } } /* LCD清屏函數(shù)：清屏從第一頁(yè)的第一列開(kāi)始，總共8頁(yè)，64列 */ void clear_screen(screen) { int x,y; select_screen(screen); //screen:0-選擇全屏，1-選擇左半屏，2-選擇右半屏 for(x=0xb8;x<0xc0;x++) //從0xb8-0xbf,共8頁(yè) { w_com(x); w_com(0x40); //列的初始地址是0x40 for(y=0;y<64;y++) { w_date(0x00); } } } /* LCD顯示漢字字庫(kù)函數(shù) */ void lcd_display_hanzi(uchar screen,uchar page,uchar col,uint mun) { //screen:選擇屏幕參數(shù)，page:選擇頁(yè)參數(shù)0-3，col:選擇列參數(shù)0-3，mun:顯示第幾個(gè)漢字的參數(shù) int a; mun=mun*32; select_screen(screen); w_com(0xb8+(page*2)); w_com(0x40+(col*16)); for ( a=0;a<16;a++) { w_date(hanzi[mun++]); } w_com(0xb8+(page*2)+1); w_com(0x40+(col*16)); for ( a=0;a<16;a++) { w_date(hanzi[mun++]); } } /* LCD顯示字符字庫(kù)函數(shù) */ void lcd_display_zifuk(uchar screen,uchar page,uchar col,uchar mun) { //screen:選擇屏幕參數(shù)，page:選擇頁(yè)參數(shù)0-3，col:選擇列參數(shù)0-7，mun:顯示第幾個(gè)漢字的參數(shù) int a; mun=mun*16; select_screen(screen); w_com(0xb8+(page*2)); w_com(0x40+(col*8)); for ( a=0;a<8;a++) { w_date(zifu[mun++]); } w_com(0xb8+(page*2)+1); w_com(0x40+(col*8)); for ( a=0;a<8;a++) { w_date(zifu[mun++]); } } /* LCD顯示數(shù)字字庫(kù)函數(shù) */ void lcd_display_shuzi(uchar screen,uchar page,uchar col,uchar mun) { //screen:選擇屏幕參數(shù)，page:選擇頁(yè)參數(shù)0-3，col:選擇列參數(shù)0-7，mun:顯示第幾個(gè)漢字的參數(shù) int a; mun=mun*16; select_screen(screen); w_com(0xb8+(page*2)); w_com(0x40+(col*8)); for ( a=0;a<8;a++) { w_date(shuzi[mun++]); } w_com(0xb8+(page*2)+1); w_com(0x40+(col*8)); for ( a=0;a<8;a++) { w_date(shuzi[mun++]); } } /* LCD初始化函數(shù) */ void lcd_init() { w_com(0x3f); //LCD開(kāi)顯示 w_com(0xc0); //LCD行初始地址，共64行 w_com(0xb8); //LCD頁(yè)初始地址，共8頁(yè) w_com(0x40); //LCD列初始地址，共64列 } /* LCD顯示主函數(shù) */ void main() { //第一行 int x; lcd_init(); //LCD初始化 clear_screen(0); //LCD清屏幕 lcd_display_shuzi(1,0,4,5); //LCD顯示數(shù)字 lcd_display_shuzi(1,0,5,1); //LCD顯示數(shù)字 lcd_display_hanzi(1,0,3,0); //LCD顯示漢字 lcd_display_hanzi(2,0,0,1); //LCD顯示漢字 //LCD字符漢字 lcd_display_hanzi(2,0,1,2); //LCD顯示漢字 //第二行 lcd_display_zifuk(1,1,2,0); //LCD顯示字符 lcd_display_zifuk(1,1,3,0); //LCD顯示字符 lcd_display_zifuk(1,1,4,0); //LCD顯示字符 lcd_display_zifuk(1,1,5,4); //LCD顯示字符 lcd_display_shuzi(1,1,6,8); //LCD顯示字符 lcd_display_shuzi(1,1,7,9); //LCD顯示字符 lcd_display_shuzi(2,1,0,5); //LCD顯示字符 lcd_display_shuzi(2,1,1,1); //LCD顯示字符 lcd_display_zifuk(2,1,2,4); lcd_display_zifuk(2,1,3,1); lcd_display_zifuk(2,1,4,2); lcd_display_zifuk(2,1,5,3); //第三行 for(x=0;x<4;x++) { lcd_display_hanzi(1,2,x,3+x); //LCD顯示漢字 } for(x=0;x<4;x++) { lcd_display_hanzi(2,2,x,7+x); //LCD顯示漢字 } //第四行 for(x=0;x<4;x++) { lcd_display_zifuk(1,3,x,5+x); //LCD顯示漢字 } lcd_display_shuzi(1,3,4,7); lcd_display_shuzi(1,3,5,5); lcd_display_shuzi(1,3,6,5); lcd_display_zifuk(1,3,7,9); lcd_display_shuzi(2,3,0,8); lcd_display_shuzi(2,3,1,9); lcd_display_shuzi(2,3,2,9); lcd_display_shuzi(2,3,3,5); lcd_display_shuzi(2,3,4,6); lcd_display_shuzi(2,3,5,8); lcd_display_shuzi(2,3,6,9); lcd_display_shuzi(2,3,7,2); while(1); /* while(1) { // LCD向上滾屏顯示 lcd_rol(); } */ }
標(biāo)簽： 12864 LCD 漢字 數(shù)字
上傳時(shí)間： 2013-11-08
上傳用戶：aeiouetla
C51 中的關(guān)鍵字關(guān)鍵字 用途 說(shuō)明auto 存儲(chǔ)種類說(shuō)明 用以說(shuō)明局部變量，缺省值為此break 程序語(yǔ)句 退出最內(nèi)層循環(huán)case 程序語(yǔ)句 Switch 語(yǔ)句中的選擇項(xiàng)char 數(shù)據(jù)類型說(shuō)明 單字節(jié)整型數(shù)或字符型數(shù)據(jù)const 存儲(chǔ)類型說(shuō)明 在程序執(zhí)行過(guò)程中不可更改的常量值continue 程序語(yǔ)句 轉(zhuǎn)向下一次循環(huán)default 程序語(yǔ)句 Switch 語(yǔ)句中的失敗選擇項(xiàng)do 程序語(yǔ)句 構(gòu)成do..while 循環(huán)結(jié)構(gòu)double 數(shù)據(jù)類型說(shuō)明 雙精度浮點(diǎn)數(shù)else 程序語(yǔ)句 構(gòu)成if..else 選擇結(jié)構(gòu)enum 數(shù)據(jù)類型說(shuō)明 枚舉extern 存儲(chǔ)種類說(shuō)明 在其他程序模塊中說(shuō)明了的全局變量flost 數(shù)據(jù)類型說(shuō)明 單精度浮點(diǎn)數(shù)for 程序語(yǔ)句 構(gòu)成for 循環(huán)結(jié)構(gòu)goto 程序語(yǔ)句 構(gòu)成goto 轉(zhuǎn)移結(jié)構(gòu)if 程序語(yǔ)句 構(gòu)成if..else 選擇結(jié)構(gòu)int 數(shù)據(jù)類型說(shuō)明 基本整型數(shù)long 數(shù)據(jù)類型說(shuō)明 長(zhǎng)整型數(shù)register 存儲(chǔ)種類說(shuō)明 使用CPU 內(nèi)部寄存的變量return 程序語(yǔ)句 函數(shù)返回short 數(shù)據(jù)類型說(shuō)明 短整型數(shù)signed 數(shù)據(jù)類型說(shuō)明 有符號(hào)數(shù)，二進(jìn)制數(shù)據(jù)的最高位為符號(hào)位sizeof 運(yùn)算符 計(jì)算表達(dá)式或數(shù)據(jù)類型的字節(jié)數(shù)static 存儲(chǔ)種類說(shuō)明 靜態(tài)變量struct 數(shù)據(jù)類型說(shuō)明 結(jié)構(gòu)類型數(shù)據(jù)swicth 程序語(yǔ)句 構(gòu)成switch 選擇結(jié)構(gòu)typedef 數(shù)據(jù)類型說(shuō)明 重新進(jìn)行數(shù)據(jù)類型定義union 數(shù)據(jù)類型說(shuō)明 聯(lián)合類型數(shù)據(jù)unsigned 數(shù)據(jù)類型說(shuō)明 無(wú)符號(hào)數(shù)數(shù)據(jù)void 數(shù)據(jù)類型說(shuō)明 無(wú)類型數(shù)據(jù)volatile 數(shù)據(jù)類型說(shuō)明 該變量在程序執(zhí)行中可被隱含地改變while 程序語(yǔ)句 構(gòu)成while 和do..while 循環(huán)結(jié)構(gòu)ANSIC 標(biāo)準(zhǔn)關(guān)鍵字關(guān)鍵字 用途 說(shuō)明bit 位標(biāo)量聲明 聲明一個(gè)位標(biāo)量或位類型的函數(shù)sbit 位標(biāo)量聲明 聲明一個(gè)可位尋址變量
標(biāo)簽： C51
上傳時(shí)間： 2013-10-08
上傳用戶：waves_0801
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
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