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//*** *** *** *** *** *** *** *** *** *** *** *** *** * // MSP-FET430x110 Demo - Software Toggle P1.0 // // Description: Toggle P1.0 by xor ing P1.0 inside of a software loop. // ACLK = n/a, MCLK = SMCLK = default DCO ~800k // // MSP430F1121 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // | P1.0|-->LED // // M. Buccini // Texas Instruments Inc. // Feb 2005 // Built with IAR Embedded Workbench Version: 3.21A
標(biāo)簽： Software MSP-FET Toggle Demo
上傳時(shí)間： 2014-01-09
上傳用戶(hù)：問(wèn)題問(wèn)題
MediaPlayer代碼，部分代碼，合適請(qǐng)用： import java.awt.* import java.awt.event.* import javax.swing.* import javax.media.* import java.io.* import java.util.* //為了導(dǎo)入Vector //import com.sun.java.swing.plaf.windows.* public class MediaPlayer extends JFrame implements ActionListener,Runnable { private JMenuBar bar //菜單條 private JMenu fileMenu,choiceMenu,aboutMenu private JMenuItem openItem,openDirItem,closeItem,about,infor private JCheckBoxMenuItem onTop private boolean top=false,loop //設(shè)定窗口是否在最前面 private Player player //Play是個(gè)實(shí)現(xiàn)Controller的接口 private File file,listFile //利用File類(lèi)結(jié)合JFileChooser進(jìn)行文件打開(kāi)操作,后則與list.ini有關(guān)
標(biāo)簽： MediaPlayer 代碼
上傳時(shí)間： 2016-07-08
上傳用戶(hù)：爺?shù)臍赓|(zhì)
ADM6993F/FXFiber to Fast Ethernet Converter (TS1000 CPE Complied) The ADM6993F/FX is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers, a three-port 10/100M Ethernet L2 switch controller, and one OAM engine to meet demanding applications, including Fiber-to-Ethernet media converters, especially the fiber to the home (FTTH) media converters. The ADM6993F/FX feature set includes link pass through (LPT), TS1000 OAM frame receiving/processing/transmitting, programmable link status LED display, various loop-back modes, and one configurable MII ports for snooping/inserting OAM frame from/to 100Fx. The ADM6993FX is the environmentally friendly “green” package version.
標(biāo)簽： 6993 ADM Converter Ethernet
上傳時(shí)間： 2014-01-01
上傳用戶(hù)：hebmuljb
This GLib version 2.16.1. GLib is the low-level core library that forms the basis for projects such as GTK+ and GNOME. It provides data structure handling for C, portability wrappers, and interfaces for such runtime functionality as an event loop, threads, dynamic loading, and an object system.
標(biāo)簽： GLib the low-level projects
上傳時(shí)間： 2013-12-19
上傳用戶(hù)：tb_6877751
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時(shí)間： 2014-11-01
上傳用戶(hù)：l254587896
A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2 sation cur rent int o t he p assive loop f ilte r during t he delay time of t he p hase f requency detect or ( PFD) , a maximum reduction of t he p hase noise by about 16dB can be achieved. Comp a red t o ot he r compensation met hods , t he tech2 nique p rop osed he re is relatively simple and easy t o implement . Key building blocks f or realizing t he noise cancel2 lation , including t he delay va riable PFD and comp ensation cur rent source , a re sp ecially designed. Bot h t he behavior level and circuit level simulation results a re p resented.
標(biāo)簽： sigma2delta compensate injecting artially
上傳時(shí)間： 2013-12-18
上傳用戶(hù)：qlpqlq
This piece of software was written as a replacement and extension for Tripwire. Tripwire is an excellent program in itself but lacks some features and is a closed product.
標(biāo)簽： Tripwire replacement extension software
上傳時(shí)間： 2014-01-25
上傳用戶(hù)：宋桃子
This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked loop (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked loop (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.
標(biāo)簽： describes unisersal document phase-lo
上傳時(shí)間： 2014-01-13
上傳用戶(hù)：hustfanenze
learning English The following appeared in a memorandum written by the vice president of Nature s Way, a chain of stores selling health food and other health-related products. "Previous experience has shown that our stores are most profitable in areas where residents are highly concerned with leading healthy lives. We should therefore build our next new store in Plainsville, which has many such residents. Plainsville merchants report that sales of running shoes and exercise clothing are at all-time highs. The local health club, which nearly closed five years ago due to lack of business, has more members than ever, and the weight training and aerobics classes are always full. We can even anticipate a new generation of customers: Plainsville s schoolchildren are required to participate in a fitness for life program, which emphasizes the benefits of regular exercise at an early age.
標(biāo)簽： memorandum following president learning
上傳時(shí)間： 2017-03-06
上傳用戶(hù)：youth25
以傳統(tǒng)的C/SDK 撰寫(xiě)Windows 程序，最大的好處是可以清楚看見(jiàn)整個(gè)程序的來(lái)龍去脈 和消息動(dòng)向，然而這些重要的動(dòng)線(xiàn)在MFC 應(yīng)用程序中卻隱晦不明，因?yàn)樗鼈儽籄pplication Framework 包起來(lái)了。這一章主要目的除了解釋MFC 應(yīng)用程序的長(zhǎng)像，也要從MFC 源代 碼中檢驗(yàn)出一個(gè)Windows 程序原本該有的程序進(jìn)入點(diǎn)（WinMain）、視窗類(lèi)別注冊(cè) （RegisterClass）、窗口產(chǎn)生（CreateWindow）、消息循環(huán)（Message Loop）、窗口函數(shù) （WindowProcedure）等等動(dòng)作，抽絲剝繭徹底了解一個(gè)MFC 程序的誕生與結(jié)束，以及生 命過(guò)程。
上傳時(shí)間： 2017-03-22
上傳用戶(hù)：athjac
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