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compiler-Inserted

  • 完整的編譯器

    完整的編譯器, compiler

    標簽: 編譯器

    上傳時間: 2015-06-17

    上傳用戶:hopy

  • contain many examples code for I2c,UART,string ,digital convert, read/write to EEprom in microchip P

    contain many examples code for I2c,UART,string ,digital convert, read/write to EEprom in microchip PIC16xx series. and the default compiler is hitech PIC16.

    標簽: microchip examples contain digital

    上傳時間: 2014-01-04

    上傳用戶:xmsmh

  • 關(guān)于FPGA流水線設(shè)計的論文 This work investigates the use of very deep pipelines for implementing circuits in

    關(guān)于FPGA流水線設(shè)計的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    標簽: investigates implementing pipelines circuits

    上傳時間: 2015-07-26

    上傳用戶:CHINA526

  • This set of simulation files performs a computational complexity performance comparison of the two m

    This set of simulation files performs a computational complexity performance comparison of the two methods mentioned in the paper. The source is ANSI-C compliant, hence any C-compiler can be used to compile the source code. It has been tested using Visual Studio.net C++ and TI code composer studio C compiler for the TMS320C6701. Note that the performance comparison may be different for different platforms.

    標簽: computational performance complexity comparison

    上傳時間: 2014-12-22

    上傳用戶:aig85

  • 電池設(shè)計的充電器 Device : AT90S2333 File name : BC.c Ver nr. : 1.0 Description : Standalone Ba

    電池設(shè)計的充電器 Device : AT90S2333 File name : BC.c Ver nr. : 1.0 Description : Standalone Battery Charger with AT90S2333 (main program) Compiler : IAR icca90 Author : Asmund Saetre / Terje Frostad / Dietmar Koenig Change log : 02.02.2000 Changed to fit Battery Charger refrence design board AS 18.02.2000 Final test and review AS

    標簽: Description Standalone Device S2333

    上傳時間: 2014-01-23

    上傳用戶:ruixue198909

  • arm-linux-gcc編譯器

    arm-linux-gcc編譯器,S3C2410開發(fā)板移植目前最新的linux2.6.14的內(nèi)核,需要使用這個編譯器編譯-arm-linux-gcc compiler, the S3C2410 development board transplant at present the newest linux2.6.14 essence, needs to use this compiler to translate ,Unix_Linux,嵌入式Linux/Embeded Linux

    標簽: arm-linux-gcc 編譯器

    上傳時間: 2015-09-03

    上傳用戶:songnanhua

  • 將GCC修改成客製化CPU的文件

    將GCC修改成客製化CPU的文件,對於需要C-COMPILER的人可以

    標簽: GCC CPU 修改

    上傳時間: 2013-12-28

    上傳用戶:zyt

  • There is an example of how to use the LDPC encode/decode with AWGN channel model in files .ldpc_de

    There is an example of how to use the LDPC encode/decode with AWGN channel model in files .\ldpc_decode.m and .\GFq\ldpc_decode.m. There are a few parity check matrices available in the code but you can use other matrices provided you have enough memory to load them. I suggest checking out matrices in Alist format available on David MacKay s web site.You will need to have access to a MEX compiler to be able to use a few functions written in C. LDPC的仿真代碼

    標簽: example channel ldpc_de encode

    上傳時間: 2013-12-03

    上傳用戶:lili123

  • Verilog and VHDL狀態(tài)機設(shè)計

    Verilog and VHDL狀態(tài)機設(shè)計,英文pdf格式 State machine design techniques for Verilog and VHDL Abstract : Designing a synchronous finite state Another way of organizing a state machine (FSM) is a common task for a digital logic only one logic block as shown in engineer. This paper will discuss a variety of issues regarding FSM design using Synopsys Design Compiler . Verilog and VHDL coding styles will be 2.0 Basic HDL coding presented. Different methodologies will be compared using real-world examples.

    標簽: Verilog VHDL and 狀態(tài)

    上傳時間: 2013-12-19

    上傳用戶:change0329

  • This design package includes reference materials for creating a USB - PS/2 combination mouse that a

    This design package includes reference materials for creating a USB - PS/2 combination mouse that auto-detects the interface and configures itself to operate on the appropriate bus. Documentation docs - Designing a low cost CY7C63723 combination mouse.pdf - application note for this design - schematic.pdf - mouse schematic Firmware Source Files src - chip.c - include file that defines CY7C63723 constants - combi.c - main source file - combi.hex - Intel hex file for programming a CY7C63723 microcontroller - combi.lst - output listing from c-compiler for use with the CYDB debugger - macros.h - defines macros used in combi.c - ps2defs.h - defines PS/2 interface constants - usb_desc.h - defines the USB descriptors - usbdefs.h - defines USB interface constants

    標簽: combination materials reference creating

    上傳時間: 2015-10-19

    上傳用戶:784533221

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