This project is created using the Keil ARM CA Compiler.
The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1
This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series.
You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
Each arc of a binary-state network has good/bad states. The system reliability, the probability
that source s communicates with sink t, can be computed in terms of minimal paths (MPs). An
MP is an ordered sequence of arcs from s to t that has no cycle. Note that a minimal path is
different from the so-called minimum path. The latter is a path with minimum cost.
This example demonstrates the use of the ADC block and PWM blocks. The generated DSP code produces the pulse waveform whose duty cycle is changing as the voltage applied to ADC input changes. The waveform period is kept constant.
SimpliciTI™ -1.0.3.exe for CC11xx and CC25xx
SimpliciTI is a simple low-power RF network protocol aimed at small (<256) RF networks. Such networks typically contain battery operated devices which require long battery life, low data rate and low duty cycle and have a limited number of nodes talking directly to each other or through an access point or range extenders. Access point and range extenders are not required but provide extra functionality such as store and forward messages. With SimpliciTI the MCU resource requirements are minimal which results in the low system cost.
SimpliciTI™ -1.0.4.exe for CC2430
SimpliciTI is a simple low-power RF network protocol aimed at small (<256) RF networks. Such networks typically contain battery operated devices which require long battery life, low data rate and low duty cycle and have a limited number of nodes talking directly to each other or through an access point or range extenders. Access point and range extenders are not required but provide extra functionality such as store and forward messages. With SimpliciTI the MCU resource requirements are minimal which results in the low system cost.
用Fourier變換求取信號的功率譜---周期圖法
用Fourier變換求取信號的功率譜---分段周期圖法
用Fourier變換求取信號的功率譜---welch方法
功率譜估計----多窗口法(multitaper method ,MTM法)
功率譜估計----最大熵法(maxmum entmpy method,MEM法)
功率譜估計----多信號分類法(multiple signal classification,music法)Fourier transform to strike a signal to the power spectrum - the cycle of plans
Fourier transform to strike a signal to the power spectrum - Sub-cycle Method
Fourier transform to strike a signal to the power spectrum --- welch method
Power spectrum estimated more than window ---- Law (multitaper method, MTM)
---- Power spectrum estimate of maximum entropy (maxmum entmpy method, MEM)
---- More than the estimated power spectrum signal classification (multiple signal classification, music)
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
Top module name : SHIFTER (File name : SHIFTER.v)
2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT.
3. Output pins: OUT [15:0].
4. Input signals generated from test pattern are latched in one cycle and are
synchronized at clock rising edge.
5. The SHIFT signal describes the shift number. The shift range is 0 to 15.
6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it
shifts input data to left.
7. When the signal SIGN is high, the input data is a signed number and it shifts with
sign extension. However, the input data is an unsigned number if the signal SIGN
is low.
8. You can only use following gates in Table I and need to include the delay
information (Tplh, Tphl) in your design.
*** *** *** *** *** *** *****
** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s
** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a
** PIC16C54 8-bit CMOS single chip microcomputer
** Revsied Version 2.0 (4/2/92).
**
** Part use = PIC16C54-XT/JW
** Note: 1) All timings are based on a reference crystal frequency of 2MHz
** which is equivalent to an instruction cycle time of 2 usec.
** 2) Address and literal values are read in octal unless otherwise
** specified.
Adaptive Coordinated Medium Access Control (AC-MAC), a contention-based Medium
Access Control protocol for wireless sensor networks. To handle the load variations in some real-time sensor applications, ACMAC
introduces the adaptive duty cycle scheme within the framework of sensor-MAC (S-MAC).