The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
LVDS、xECL、CML（低電壓差分信號傳輸、發射級耦合邏輯、電流模式邏輯）………4多點式低電壓差分信號傳輸(M-LVDS) ……………………………………………………8數字隔離器 ………………………………………………………………………………10RS-485/422 …………………………………………………………………………………11RS-232………………………………………………………………………………………13UART（通用異步收發機）…………………………………………………………………16CAN（控制器局域網）……………………………………………………………………18FlatLinkTM 3G ………………………………………………………………………………19SerDes（串行G 比特收發機及LVDS）……………………………………………………20DVI（數字視頻接口）/PanelBusTM ………………………………………………………22TMDS（最小化傳輸差分信號） …………………………………………………………24USB 集線器控制器及外設器件 …………………………………………………………25USB 接口保護 ……………………………………………………………………………26USB 電源管理 ……………………………………………………………………………27PCI Express® ………………………………………………………………………………29PCI 橋接器 …………………………………………………………………………………33卡總線 (CardBus) 電源開關 ………………………………………………………………341394 (FireWire®, 火線®) ……………………………………………………………………36GTLP (Gunning Transceiver Logic Plus，體效應收發機邏輯+) ………………………………39VME（Versa Module Eurocard）總線 ………………………………………………………41時鐘分配電路 ……………………………………………………………………………42交叉參考指南 ……………………………………………………………………………43器件索引 …………………………………………………………………………………47技術支持 …………………………………………………………………………………48 德州儀器（TI）為您提供了完備的接口解決方案，使得您的產品別具一格，并加速了產品面市。憑借著在高速、復合信號電路、系統級芯片 (system-on-a-chip ) 集成以及先進的產品開發工藝方面的技術專長，我們將能為您提供硅芯片、支持工具、軟件和技術文檔，使您能夠按時的完成并將最佳的產品推向市場，同時占據一個具有競爭力的價格。本選擇指南為您提供與下列器件系列有關的設計考慮因素、技術概述、產品組合圖示、參數表以及資源信息：
上傳時間： 2013-10-21
上傳用戶：Jerry_Chow
介紹了SoPC（System on a Programmable Chip）系統的概念和特點，給出了基于PLB總線的異步串行通信（UART）IP核的硬件設計和實現。通過將設計好的UART IP核集成到SoPC系統中加以驗證，證明了所設計的UART IP核可以正常工作。該設計方案為其他基于SoPC系統IP核的開發提供了一定的參考。
上傳時間： 2013-11-12
上傳用戶：894448095
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時間： 2013-11-21
上傳用戶：不懂夜的黑
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標簽： Base-Station Applications Single-Chip Transceiver
上傳時間： 2013-11-05
上傳用戶：超凡大師
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
標簽： Solutions Analog Altera FPGAs
上傳時間： 2013-10-27
上傳用戶：fredguo
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
PQP is a library for performing three types of proximity queries on a pair of geometric models composed of triangles:
標簽： performing geometric proximity library
上傳時間： 2014-01-13
上傳用戶：love_stanford
uClinux on ARM7TDMI(ppt)
上傳時間： 2013-12-11
上傳用戶：shizhanincc
TheTool is highy customizable map editor(based on QT) which can be extended via LUA scripts. A first implentation is ready and can be published to the public. The editor is the perfect tool who wants to design some 3d games but don t have time to write
標簽： customizable extended TheTool scripts
上傳時間： 2013-12-12
上傳用戶：lanwei
