Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
標簽： Spartan-DSP Virtex FPGAs Ap
上傳時間： 2013-10-23
上傳用戶：raron1989
This application note describes how to decode standard DTMF tones using the minimum number of external discrete components and a PIC. The two examples use a PIC which has an 8 bit timer and either a comparator or an ADC, although it can be modified for use on a PIC which has only digital I/O. The Appendices have example code for the 16C662 (with comparator) and 16F877 (using the ADC). As the majority of the Digital Signal Processing is done in software, little is required in the way of external signal conditioning. Software techniques are used to model the individual elements of a DTMF Decoder IC.
上傳時間： 2013-11-21
上傳用戶：zhaoke2005
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上傳時間： 2013-11-07
上傳用戶：jasson5678
6小時學會labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標簽： labview
上傳時間： 2013-10-13
上傳用戶：zjwangyichao
3 FPGA設計流程 完整的FPGA 設計流程包括邏輯電路設計輸入、功能仿真、綜合及時序分析、實現、加載配置、調試。FPGA 配置就是將特定的應用程序設計按FPGA設計流程轉化為數據位流加載到FPGA 的內部存儲器中，實現特定邏輯功能的過程。由于FPGA 電路的內部存儲器都是基于RAM 工藝的，所以當FPGA電路電源掉電后，內部存儲器中已加載的位流數據將隨之丟失。所以，通常將設計完成的FPGA 位流數據存于外部存儲器中，每次上電自動進行FPGA電路配置加載。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，FPGA的配置模式有四種方案可選擇：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通過芯片上的一組專/ 復用引腳信號完成的，主要配置功能信號如下： (1)M0、M1、M2：下載配置模式選擇; (2)CLK：配置時鐘信號; (3)done：顯示配置狀態、控制器件啟動;
上傳時間： 2013-11-18
上傳用戶：oojj
UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
上傳時間： 2013-11-02
上傳用戶：18862121743
pdnMesh is an automatic mesh generator and solver for Finite Element problems. It will also do post-processing to generate contour plots and Postscript printouts. GUI support using GTK or MFC (Win32) is available. The problem definition can be done in any form and given to pdnMesh as an input data file. Drawing Exchange Format (DXF) files can be directly imported to pdnmesh. The quality and the coarseness of the mesh can be controlled by giving input parameters.
標簽： automatic generator problems pdnMesh
上傳時間： 2013-12-19
上傳用戶：cuibaigao
XMDS is a code generator that integrates equations. You write them down in human readable form in a XML file, and it goes away and writes and compiles a C++ program that integrates those equations as fast as it can possibly be done in your architecture.
標簽： integrates generator equations readable
上傳時間： 2014-11-27
上傳用戶：hebmuljb
項目描述: Trickster Streaming Server is a pure Perl MP3 streaming server with a simple Web interface that allows you to manipulate and browse the queue. The queue management API is done in a fairly simple UNIX manner, and can be easily extended. Trickster Streaming Server是一個具有簡單 Web接口的純 Perl MP3流服務器，它讓你操作并瀏覽隊列。這個隊列管理 API 用一種相當簡單的UNIX方式來做，并能被容易的擴展。
標簽： Trickster Streaming interface streaming
上傳時間： 2013-12-13
上傳用戶：lz4v4
This firmware translates a PS/2 mouse to a USB mouse. The translator firmware is entirely interrupt driven (with the exception of sending the data via USB to the host.) An interrupt is generated when the PS/2 start bit is received, at which time the firmware will begin its receive routine. In addition to this interrupt, every 168ms a timer overflow interrupts the main program and implements one state of the mouse state machine. This state machine handles sending bytes to and translating bytes received from the PS/2 mouse automatically. All of this is done in the background while the main program runs in the foreground. The only operation that the main program implements is sending mouse data to the PC via USB.
標簽： firmware mouse translates translator
上傳時間： 2015-04-26
上傳用戶：cuiyashuo
