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用外部設備設置32位微控制器TriCore的中斷的指令及方法

The Infineon TriCore provides an Interrupt System with a high safety standard. Thisdocument contains some instructions on how to initiate an Interrupt from an externaldevice. First it will show you how to trigger an Interrupt Service Request by an impulseon Port 0 or Port 1. Then in the second part of the document you can find hints how todebounce impulses to enable the use of a simple switch as input device.Authors: Thomas Bliem, CQ Nguyen / Infineon SMI MD Apps

標簽： TriCore 外部設備中斷微控制器

上傳時間： 2013-11-05

上傳用戶：uuuuuuu
3.3v看門狗芯片

The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.

標簽： 3.3 看門狗芯片

上傳時間： 2013-10-22

上傳用戶：taiyang250072
便攜式超聲系統中的Xilinx器件

There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.

標簽： Xilinx 便攜式超聲系統器件

上傳時間： 2013-10-26

上傳用戶：liulinshan2010
WP312-Xilinx新一代28nm FPGA技術簡介

Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

標簽： Xilinx FPGA 312 WP

上傳時間： 2014-12-28

上傳用戶：zhang97080564
各種功能的計數器實例（VHDL源代碼）

各種功能的計數器實例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;

標簽： VHDL 計數器源代碼

上傳時間： 2014-11-30

上傳用戶：半熟1994
lpc2292/lpc2294 pdf datasheet

The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.

標簽： lpc datasheet 2292 2294

上傳時間： 2014-12-30

上傳用戶：aysyzxzm
hspice 2007下載 download

解壓密碼：www.elecfans.com 隨著微電子技術的迅速發展以及集成電路規模不斷提高，對電路性能的設計要求越來越嚴格，這勢必對用于大規模集成電路設計的EDA 工具提出越來越高的要求。自1972 年美國加利福尼亞大學柏克萊分校電機工程和計算機科學系開發的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC Emphasis）誕生以來，為適應現代微電子工業的發展，各種用于集成電路設計的電路模擬分析工具不斷涌現。HSPICE 是Meta-Software 公司為集成電路設計中的穩態分析，瞬態分析和頻域分析等電路性能的模擬分析而開發的一個商業化通用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它電路分析軟件的基礎上，又加入了一些新的功能，經過不斷的改進，目前已被許多公司、大學和研究開發機構廣泛應用。HSPICE 可與許多主要的EDA 設計工具，諸如Candence,Workview 等兼容，能提供許多重要的針對集成電路性能的電路仿真和設計結果。采用HSPICE 軟件可以在直流到高于100MHz 的微波頻率范圍內對電路作精確的仿真、分析和優化。在實際應用中， HSPICE能提供關鍵性的電路模擬和設計方案，并且應用HSPICE進行電路模擬時，其電路規模僅取決于用戶計算機的實際存儲器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.

標簽： download hspice 2007

上傳時間： 2013-11-10

上傳用戶：123312
便攜式超聲系統中的Xilinx器件

There has long been a need for portable ultrasoundsystems that have good resolution at affordable costpoints. Portable systems enable healthcare providersto use ultrasound in remote locations such asdisaster zones, developing regions, and battlefields,where it was not previously practical to do so.

標簽： Xilinx 便攜式超聲系統器件

上傳時間： 2015-01-01

上傳用戶：hfnishi
WP312-Xilinx新一代28nm FPGA技術簡介

Xilinx Next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

標簽： Xilinx FPGA 312 WP

上傳時間： 2013-12-07

上傳用戶：bruce
各種功能的計數器實例（VHDL源代碼）

各種功能的計數器實例（VHDL源代碼）:ENTITY counters IS PORT ( d : IN INTEGER RANGE 0 TO 255; clk : IN BIT; clear : IN BIT; ld : IN BIT; enable : IN BIT; up_down : IN BIT; qa : OUT INTEGER RANGE 0 TO 255; qb : OUT INTEGER RANGE 0 TO 255; qc : OUT INTEGER RANGE 0 TO 255; qd : OUT INTEGER RANGE 0 TO 255; qe : OUT INTEGER RANGE 0 TO 255; qf : OUT INTEGER RANGE 0 TO 255; qg : OUT INTEGER RANGE 0 TO 255; qh : OUT INTEGER RANGE 0 TO 255; qi : OUT INTEGER RANGE 0 TO 255;

標簽： VHDL 計數器源代碼

上傳時間： 2013-10-09

上傳用戶：松毓336