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This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標簽：
pci
PCB
設計規范
上傳時間：
2013-10-15
上傳用戶：busterman
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特點(FEATURES) 精確度0.1%滿刻度 (Accuracy 0.1%F.S.) 可作各式數學演算式功能如:A+B/A-B/AxB/A/B/A&B(Hi or Lo)/|A| (Math functioA+B/A-B/AxB/A/B/A&B(Hi&Lo)/|A|/etc.....) 16 BIT 類比輸出功能(16 bit DAC isolating analog output function) 輸入/輸出1/輸出2絕緣耐壓2仟伏特/1分鐘(Dielectric strength 2KVac/1min. (input/output1/output2/power)) 寬范圍交直流兩用電源設計(Wide input range for auxiliary power) 尺寸小,穩定性高(Dimension small and High stability)
標簽：
微電腦
數學演算
輸出
隔離傳送器
上傳時間：
2013-11-24
上傳用戶：541657925
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Abstract: A resistive feedback network is often used to set the output voltage of a power supply. A mechanical potentiometer (pot)conveniently solves the problem of adjusting a power supply. For easier automatic calibration, a mechanical pot can be replaced witha digital pot. This application note presents a calibration solution that uses a digital pot, because digipots are smaller, do not movewith age or vibration, and can be recalibrated remotely. This proposed solution reduces the susceptibility of the system to thetolerance of the digital pot's end-to-end resistance, making the solution optimal fordesigners. This application note also explainssome of the equations required to calculate the resistor chain values and to use a digital pot in this way. A spreadsheet withstandard reisistor values is available for easy calculations.
標簽：
電源供應器
數字電位器
應用筆記
校準
上傳時間：
2013-10-31
上傳用戶：caiguoqing
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/*--------- 8051內核特殊功能寄存器 -------------*/
sfr ACC = 0xE0; //累加器
sfr B = 0xF0; //B 寄存器
sfr PSW = 0xD0; //程序狀態字寄存器
sbit CY = PSW^7; //進位標志位
sbit AC = PSW^6; //輔助進位標志位
sbit F0 = PSW^5; //用戶標志位0
sbit RS1 = PSW^4; //工作寄存器組選擇控制位
sbit RS0 = PSW^3; //工作寄存器組選擇控制位
sbit OV = PSW^2; //溢出標志位
sbit F1 = PSW^1; //用戶標志位1
sbit P = PSW^0; //奇偶標志位
sfr SP = 0x81; //堆棧指針寄存器
sfr DPL = 0x82; //數據指針0低字節
sfr DPH = 0x83; //數據指針0高字節
/*------------ 系統管理特殊功能寄存器 -------------*/
sfr PCON = 0x87; //電源控制寄存器
sfr AUXR = 0x8E; //輔助寄存器
sfr AUXR1 = 0xA2; //輔助寄存器1
sfr WAKE_CLKO = 0x8F; //時鐘輸出和喚醒控制寄存器
sfr CLK_DIV = 0x97; //時鐘分頻控制寄存器
sfr BUS_SPEED = 0xA1; //總線速度控制寄存器
/*----------- 中斷控制特殊功能寄存器 --------------*/
sfr IE = 0xA8; //中斷允許寄存器
sbit EA = IE^7; //總中斷允許位
sbit ELVD = IE^6; //低電壓檢測中斷控制位
8051
標簽：
80C51
特殊功能寄存器
地址
上傳時間：
2013-10-30
上傳用戶：yxgi5
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在理論分析循環碼編碼和譯碼基本原理的基礎上，提出了基于單片機系統的(24，16)循環碼軟件實現編碼、譯碼的方案。仿真結果表明(24，16)循環碼能有效地克服來自通訊信道的干擾，保證數據通信的可靠及系統的穩定，使誤碼率大幅度降低。本論文對(24，16)循環碼的研究結果表明，可以有效地降低錯誤概率和提高系統的吞吐量，實現糾錯僅需要在接收端增加有限的存儲空間和計算復雜度，具有一定的實用價值。
Abstract:
Based on analyzing the theory of encoding and decoding of cyclic code， this paper showed the schemes of encoding and decoding of(24，16)cyclic code by the software and based on microcontroller. Simulation results show that using (24，16) cyclic codes can effectively overcome the interference from communication channel， ensure the reliability and stability of data communication systems， and reduce the bit error rate greatly. The results of this paper show that by using the (24，16) cyclic code， the error rate can be reduced and the system throughput can be improved. Meanwhile， the system only needs to enlarge limited storage space and computation the complexity at the receiving end to realize error correction. Thus the (24，16) cyclic code has a practical value.
標簽：
24
16
單片機系統
循環碼
上傳時間：
2013-11-09
上傳用戶：gaoliangncepu
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摘要: 串行傳輸技術具有更高的傳輸速率和更低的設計成本, 已成為業界首選, 被廣泛應用于高速通信領域。提出了一種新的高速串行傳輸接口的設計方案, 改進了Aurora 協議數據幀格式定義的弊端, 并采用高速串行收發器Rocket I/O, 實現數據率為2.5 Gbps的高速串行傳輸。關鍵詞: 高速串行傳輸; Rocket I/O; Aurora 協議
為促使FPGA 芯片與串行傳輸技術更好地結合以滿足市場需求, Xilinx 公司適時推出了內嵌高速串行收發器RocketI/O 的Virtex II Pro 系列FPGA 和可升級的小型鏈路層協議———Aurora 協議。Rocket I/O支持從622 Mbps 至3.125 Gbps的全雙工傳輸速率, 還具有8 B/10 B 編解碼、時鐘生成及恢復等功能, 可以理想地適用于芯片之間或背板的高速串行數據傳輸。Aurora 協議是為專有上層協議或行業標準的上層協議提供透明接口的第一款串行互連協議, 可用于高速線性通路之間的點到點串行數據傳輸, 同時其可擴展的帶寬, 為系統設計人員提供了所需要的靈活性[4]。但該協議幀格式的定義存在弊端,會導致系統資源的浪費。本文提出的設計方案可以改進Aurora 協議的固有缺陷,提高系統性能, 實現數據率為2.5 Gbps 的高速串行傳輸, 具有良好的可行性和廣闊的應用前景。
標簽：
Rocket
2.5
高速串行
收發器
上傳時間：
2013-11-06
上傳用戶：smallfish
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摘要: 串行傳輸技術具有更高的傳輸速率和更低的設計成本, 已成為業界首選, 被廣泛應用于高速通信領域。提出了一種新的高速串行傳輸接口的設計方案, 改進了Aurora 協議數據幀格式定義的弊端, 并采用高速串行收發器Rocket I/O, 實現數據率為2.5 Gbps的高速串行傳輸。關鍵詞: 高速串行傳輸; Rocket I/O; Aurora 協議
為促使FPGA 芯片與串行傳輸技術更好地結合以滿足市場需求, Xilinx 公司適時推出了內嵌高速串行收發器RocketI/O 的Virtex II Pro 系列FPGA 和可升級的小型鏈路層協議———Aurora 協議。Rocket I/O支持從622 Mbps 至3.125 Gbps的全雙工傳輸速率, 還具有8 B/10 B 編解碼、時鐘生成及恢復等功能, 可以理想地適用于芯片之間或背板的高速串行數據傳輸。Aurora 協議是為專有上層協議或行業標準的上層協議提供透明接口的第一款串行互連協議, 可用于高速線性通路之間的點到點串行數據傳輸, 同時其可擴展的帶寬, 為系統設計人員提供了所需要的靈活性[4]。但該協議幀格式的定義存在弊端,會導致系統資源的浪費。本文提出的設計方案可以改進Aurora 協議的固有缺陷,提高系統性能, 實現數據率為2.5 Gbps 的高速串行傳輸, 具有良好的可行性和廣闊的應用前景。
標簽：
Rocket
2.5
高速串行
收發器
上傳時間：
2013-10-13
上傳用戶：lml1234lml
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This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標簽：
pci
PCB
設計規范
上傳時間：
2014-01-24
上傳用戶：s363994250
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題目：利用條件運算符的嵌套來完成此題：學習成績>=90分的同學用A表示，60-89分之間的用B表示，60分以下的用C表示。 1.程序分析：(a>b)?a:b這是條件運算符的基本例子。
標簽：
gt
90
運算符
嵌套
上傳時間：
2015-01-08
上傳用戶：lifangyuan12
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RSA算法 :首先, 找出三個數, p, q, r, 其中 p, q 是兩個相異的質數, r 是與 (p-1)(q-1) 互質的數...... p, q, r 這三個數便是 person_key，接著, 找出 m, 使得 r^m == 1 mod (p-1)(q-1)..... 這個 m 一定存在, 因為 r 與 (p-1)(q-1) 互質, 用輾轉相除法就可以得到了..... 再來, 計算 n = pq....... m, n 這兩個數便是 public_key ，編碼過程是, 若資料為 a, 將其看成是一個大整數, 假設 a < n.... 如果 a >= n 的話, 就將 a 表成 s 進位 (s
標簽：
person_key
RSA
算法
上傳時間：
2013-12-14
上傳用戶：zhuyibin
