This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時間： 2013-10-31
上傳用戶：yy_cn
enter——選取或啟動 esc——放棄或取消 f1——啟動在線幫助窗口 tab——啟動浮動圖件的屬性窗口 pgup——放大窗口顯示比例 pgdn——縮小窗口顯示比例 end——刷新屏幕 del——刪除點取的元件（1個） ctrl+del——刪除選取的元件（2個或2個以上） x+a——取消所有被選取圖件的選取狀態 x——將浮動圖件左右翻轉 y——將浮動圖件上下翻轉 space——將浮動圖件旋轉90度 crtl+ins——將選取圖件復制到編輯區里 shift+ins——將剪貼板里的圖件貼到編輯區里 shift+del——將選取圖件剪切放入剪貼板里 alt+backspace——恢復前一次的操作 ctrl+backspace——取消前一次的恢復 crtl+g——跳轉到指定的位置 crtl+f——尋找指定的文字
上傳時間： 2013-11-01
上傳用戶：a296386173
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
RemoteWAP is a Remote Administration Tool for any Operating System that can support the Java Virtual Machine. It has been designed for anyone who wishes to have complete control of there OS anywhere by using a WAP enabled Mobile Phone. RemoteWAP is developed using Java and WML for the client mobile phone front-end pages. RemoteWAP has a Java Swing-GUI to allow for easy control. Future releases will have a Command Line Interface for quick use
標簽： Administration RemoteWAP Operating Virtual
上傳時間： 2015-02-01
上傳用戶：exxxds
A simple utility to split a concatenated vCard format file into separate files (IETF RFC 2426 - vCard MIME Directory Profile). It splits on the BEGIN:VCARD and end:VCARD tags. It was created to help import a Lotus Organizer export file into Palm Desktop
標簽： concatenated separate utility simple
上傳時間： 2013-12-20
上傳用戶：gxf2016
c語言編程規范Style guidelines and programming practices for C/C++ code for Dynamic Software Solutions. Use the checklist at the end of this document prior to submitting code for peer review.
標簽： programming guidelines Solutions for
上傳時間： 2014-07-11
上傳用戶：aeiouetla
此代碼可以實現以下功能 使用wordappalication 組件，代碼如下 啟動Word時用如下代碼： begin try Wordapplication.Connect except MessageDlg(’Word may not be installed’, mtError, [mbOk], 0) Abort end Wordapplication.Visible := True WordApplication.Caption := ’Delphi automation’ end
標簽： wordappalication 代碼
上傳時間： 2014-01-22
上傳用戶：Divine
此為編譯原理實驗報告 學習消除文法左遞規算法，了解消除文法左遞規在語法分析中的作用 內含 設計算法 目的 源碼 等等.... 算法:消除左遞歸算法為: （1）把文法G的所有非終結符按任一種順序排列成P1,P2,…Pn 按此順序執行 （2）FOR i:=1 TO n DO BEGIN FOR j:=1 DO 把形如Pi→Pjγ的規則改寫成 Pi→δ1γ δ2γ … δkγ。其中Pj→δ1 δ2 … δk是關于Pj的所有規則； 消除關于Pi規則的直接左遞歸性 end （3）化簡由（2）所得的文法。即去除那些從開始符號出發永遠無法到達的非終結符的 產生規則。
上傳時間： 2015-03-29
上傳用戶：極客
TOYFDTD1 is a stripped-down minimalist, 3D FDTD code demonstrating the basic tasks in implementing a simple 3D FDTD simulation. An idealized rectangular waveguide is modeled by treating the interior of the mesh as free space and enforcing PEC conditions on the faces of the mesh. A simplified plane wave source is inserted at one end. First released 12 April 1999. Version 1.03 released 2 December 1999.
標簽： demonstrating stripped-down implementing minimalist
上傳時間： 2013-12-21
上傳用戶：無聊來刷下
