-
PCI ExpressTM Architecture
Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistQuestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.
標(biāo)簽：
Architecture
ExpressTM
PCI
上傳時(shí)間：
2013-11-03
上傳用戶：gy592333
-
隨著系統(tǒng)設(shè)計(jì)復(fù)雜性和集成度的大規(guī)模提高，電子系統(tǒng)設(shè)計(jì)師們正在從事100MHZ以上的電路設(shè)計(jì)，總線的工作頻率也已經(jīng)達(dá)到或者超過50MHZ，有一大部分甚至超過100MHZ。目前約80% 的設(shè)計(jì)的時(shí)鐘頻率超過50MHz，將近50% 以上的設(shè)計(jì)主頻超過120MHz，有20%甚至超過500M。當(dāng)系統(tǒng)工作在50MHz時(shí)，將產(chǎn)生傳輸線效應(yīng)和信號(hào)的完整性問題；而當(dāng)系統(tǒng)時(shí)鐘達(dá)到120MHz時(shí)，除非使用高速電路設(shè)計(jì)知識(shí)，否則基于傳統(tǒng)方法設(shè)計(jì)的PCB將無法工作。因此，高速電路信號(hào)質(zhì)量仿真已經(jīng)成為電子系統(tǒng)設(shè)計(jì)師必須采取的設(shè)計(jì)手段。只有通過高速電路仿真和先進(jìn)的物理設(shè)計(jì)軟件，才能實(shí)現(xiàn)設(shè)計(jì)過程的可控性。傳輸線效應(yīng)基于上述定義的傳輸線模型，歸納起來，傳輸線會(huì)對(duì)整個(gè)電路設(shè)計(jì)帶來以下效應(yīng)。 · 反射信號(hào)Reflected signals · 延時(shí)和時(shí)序錯(cuò)誤Delay & Timing errors · 過沖(上沖/下沖)Overshoot/Undershoot · 串?dāng)_Induced Noise (or crosstalk) · 電磁輻射EMI radiation
標(biāo)簽：
高速電路
傳輸線
效應(yīng)分析
上傳時(shí)間：
2013-11-16
上傳用戶：lx9076
-
Abstract: Rail splitting is creating an artificial virtual ground as a reference voltage. It is used to set the signalto match the op amp's "sweet spot." An op amp has the most linear- and distortion-free qualities at that sweetspot. Typically, the sweet spot occurs near the center between the single power rail and ground. In the case ofa number of signals, the virtual ground can control channel DC errors when multiplexing or switching thesignals.
標(biāo)簽：
電源調(diào)整
虛擬地
上傳時(shí)間：
2013-10-23
上傳用戶：wushengwu
-
Important Notice SUNPLUS INNOVATION TECHNOLOGY INC. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS INNOVATION TECHNOLOGY INC. is believed to be accurate and reliable. However, SUNPLUS INNOVATION TECHNOLOGY INC.makes no warranty for any errors which may appear in this document. Contact SUNPLUS INNOVATION TECHNOLOGY INC.to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS INNOVATION TECHNOLOGY INC. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUSIT products are not authorized for use as critical components in life support systems or aviation systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of SunplusIT
標(biāo)簽：
SUNPLUSIT
Q-Writer
編程工具
使用說明書
上傳時(shí)間：
2013-10-13
上傳用戶：brain kung
-
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
標(biāo)簽：
3.3
看門狗
芯片
上傳時(shí)間：
2013-10-22
上傳用戶：taiyang250072
-
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you
solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,
distribute, republish, download, display, post, or transmit the Documentation in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.
Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx
assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections
or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be
provided to you in connection with the Information.
標(biāo)簽：
CPLD
上傳時(shí)間：
2013-10-22
上傳用戶：李哈哈哈
-
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
標(biāo)簽：
PCI
總線
上傳時(shí)間：
2013-11-01
上傳用戶：KSLYZ
-
We all know the benefits of using FieldProgrammable Gate Arrays (FPGAs): no NRE, nominimum order quantities, and faster time-tomarket.In an ideal world, designs would never needto be changed because of design errors, but we allknow that sometimes this is necessary.
標(biāo)簽：
276
WP
可編程
測(cè)試
上傳時(shí)間：
2013-11-04
上傳用戶：leixinzhuo
-
The information in this specification is subject to change without notice.Use of this specification for product design requires an executed license agreement from the CompactFlashAssociation.The CompactFlash Association shall not be liable for technical or editorial errors or omissions contained herein; norfor incidental or consequential damages resulting from the furnishing, performance, or use of this material.All parts of the CompactFlash Specification are protected by copyright law and all rights are reserved. Thisdocumentation may not, in whole or in part, be copied, photocopied, reproduced, translated, or reduced to anyelectronic medium or machine readable form without prior consent, in writing, from the CompactFlash Association.The CFA logo is a trademark of the CompactFlash Association.Product names mentioned herein are for identification purposes only and may be trademarks and/or registeredtrademarks of their respective companies.© 1998-99, CompactFlash Association. All rights reserved.
標(biāo)簽：
技術(shù)資料
上傳時(shí)間：
2013-10-08
上傳用戶：stewart·
-
ORCAD在使用的時(shí)候總會(huì)出現(xiàn)這樣或那樣的問題…但下這個(gè)問題比較奇怪…在ORCAD中無法輸出網(wǎng)表…彈出下面的錯(cuò)誤….這種問題很是奇怪…Netlist Format: tango.dllDesign Name: D:\EDA_PROJECT\PROTEL99SE\YK\SV3200\MAIN.DSNERROR [NET0021] Cannot get part.[FMT0024] Ref-des not found. Possible Logical/Physical annotation conflict.[FMT0018] errors processing intermediate file找了一天沒找到問題…終于在花了N多時(shí)間后發(fā)現(xiàn)問題所在…其實(shí)這個(gè)問題就是不要使用ORCAD PSPICE 庫(kù)里面的元件來畫電路圖…實(shí)際中我是用了PSPICE里面和自己制作的二種電阻和電容混合在一起…就會(huì)出現(xiàn)這種問題…
標(biāo)簽：
orcad
無法輸出
網(wǎng)表
上傳時(shí)間：
2013-11-21
上傳用戶：zaocan888
