This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
Logger iButton devices have gained a lot of popularity with researchers. Although free evaluation software is easy to use and welldocumented, the choices and inputs that need to be made can sometimes be challenging. This application note explains technicalterms that are common with temperature logger iButtons and how they relate to each other. Additionally, it presents an algorithm tohelp users choose the necessary input parameters, including the sample rate based on a user's needs and the available memory tostore the data.
LPC2148 USB Audio Device Example
This USB example project implements an USB Audio Device that connects via the USB interface to the PC. It may be used on the following devices:
LPC2141
LPC2142
LPC2144
LPC2146
LPC2148
An USB Audio Device (HID) does not require any special USB driver, since the USB Audio support is already built into Windows 2000 and Windows XP. Therefore USB Audio devices can be directly connected to the computer. This example project is designed to work with Keil MCB2140 evaluation Board.
Refer to Running USBAudio for information on how to operate this example project.
This project is created using the Keil ARM CA Compiler.
The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1
This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series.
You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
This package contains example software and associated documentation for the
ColdFire MCF5249 microprocessor. The software includes sample processor
initialization routines for the MCF5249 running a M5249C3 evaluation board as
well as the following sample applications:
simple - empty application template
fat - factory acceptance test for the M5249C3
The software has currently been built and tested under Metrowerks CodeWarrior
uC/OS-II Notes from Nohau Corporation
The code associated with this readme.txt file is provided "as is".
The code was written with the intention of creating a functional
RTOS demo for the Nohau evaluation boards that can run a MicroBlaze
core. You can use this code for any and all of your projects, as
you see fit. Nohau Corporation does not warrant that the code is
bug-free, and will provide no support for this RTOS port.
In a preemptive priority based RTOS, priority inversion
problem is among the major sources of deadline
violations. Priority inheritance protocol is one of the
approaches to reduce priority inversion. Unfortunately,
RTOS like uC/OS can’t support priority inheritance
protocol since it does not allow kernel to have multiple
tasks at the same priority. Although it has different ways
to avoid priority inversion such as priority ceiling
protocol, developers still have some difficulties in
programming real time applications with it. In this paper,
we redesign the uC/OS kernel to provide the ability to
support round robin scheduling and implement priority
inheritance semaphore on the modified kernel. As result,
we port new kernel with priority inheritance semaphore to
evaluation board, and evaluate the execution time of each
of the kernel service as well as verify the operations of
our implementation.
