The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
超導限流器作為非線性元件短路電流限制器，具有體積小、重量輕、損耗小的特點。飽和鐵心型超導限流器（Saturated Iron Core Superconductive fault Current Limiter--SICSFCL）作為超導限流器中具有技術優勢，可適用于高壓電網的限流器必將得到廣泛應用，本文通過對SICSFCL工作原理分析，運用Ansoft軟件搭建220 kV/800A型號的SICSFCL，分析其不同外部短路電流下工作特性。表明SICSFCL對于220 kV電網短路電流具有良好的限制作用，可滿足電網中電氣設備的安全可靠運行要求。
上傳時間： 2013-11-12
上傳用戶：xiaohanhaowei
這是一個模擬第3類模式地震波的matlab腳本。 This a collection of Matlab scripts that solve the antiplane (mode III) earthquake dynamic problem with slip-weakening friction, on a 1D fault embedded in a 2D homogeneous elastic unbounded medium. The problem is formulated as a boundary integral equation and the elastodynamic kernels are analytically derived in the spectral domain (spatial wavenumber). The method is explained e.g. by Morrysey and Geubelle (1997), and has been improved and extensively used by Nadia Lapusta, Alain Cochard, etc.
標簽： collection antiplane scripts matlab
上傳時間： 2013-12-26
上傳用戶：遠遠ssad
The software implements particle filtering and Rao Blackwellised particle filtering for conditionally Gaussian Models. The RB algorithm can be interpreted as an efficient stochastic mixture of Kalman filters. The software also includes efficient state-of-the-art resampling routines. These are generic and suitable for any application. For details, please refer to Rao-Blackwellised Particle Filtering for fault Diagnosis and On Sequential Simulation-Based Methods for Bayesian Filtering After downloading the file, type "tar -xf demo_rbpf_gauss.tar" to uncompress it. This creates the directory webalgorithm containing the required m files. Go to this directory, load matlab and run the demo.
標簽： filtering particle Blackwellised conditionall
上傳時間： 2014-12-05
上傳用戶：410805624
三星公司官方 GIVEIO.SYS源代碼下載。 In windows NT/2000/XP, any application can’t access the I/O such as the parallel port. So, GIVEIO.SYS enables SJF.exe to access the parallel port without any memory fault. In windows 95/98, GIVEIO.SYS isn’t needed.
標簽： application the windows GIVEIO
上傳時間： 2014-01-11
上傳用戶：yd19890720
TIDA-00807 OH fault Indicator Software (Rev. A)-故障指示器TI官方例子
上傳時間： 2018-06-24
上傳用戶：zxw584
The SP2526A device is a dual +3.0V to +5.5V USB Supervisory Power Control Switch ideal for self-powered and bus-powered Universal Serial Bus (USB) applications. Each switch has low on-resistance (110mΩ typical) and can supply 500mA minimum. The fault currents are limited to 1.0A typical and the flag output pin for each switch is available to indicate fault conditions to the USB controller. The thermal shutdown feature will prevent damage to the device when subjected to excessive current loads. The undervoltage lockout feature will ensure that the device will remain off unless there is a valid input voltage present.
標簽： High-Side Switch Power Dual USB
上傳時間： 2019-03-06
上傳用戶：bhitr
The BTS5016SDA is a one channel high-side power switch in PG-TO252-5-11 package providing embedded protective functions. The power transistor is built by a N-channel vertical power MOSFET with charge pump. The design is based on Smart SIPMOS chip on chip technology. The BTS5016SDA has a current controlled input and offers a diagnostic feedback with load current sense and a defined fault signal in case of overload operation, overtemperature shutdown and/or short circuit shutdown.
上傳時間： 2019-03-27
上傳用戶：guaixiaolong
This book addresses two aspects of network operation quality; namely, resource management and fault management. Network operation quality is among the functions to be fulfilled in order to offer quality of service, QoS, to the end user. It is characterized by four parameters: – packet loss; – delay; – jitter, or the variation of delay over time; – availability. Resource management employs mechanisms that enable the first three parameters to be guaranteed or optimized. fault management aims to ensure continuity of service.
標簽： Ethernet Networks MPLS and IP
上傳時間： 2020-05-27
上傳用戶：shancjb
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標簽： RTL verilog hdl
上傳時間： 2022-03-21
上傳用戶：canderile
