WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上傳時間： 2013-11-07
上傳用戶：defghi010
很多不同的廠家生產各種型號的計算機，它們運行完全不同的操作系統，但TCP.IP協議族允許它們互相進行通信。這一點很讓人感到吃驚，因為它的作用已遠遠超出了起初的設想。T C P / I P起源于6 0年代末美國政府資助的一個分組交換網絡研究項目，到9 0年代已發展成為計算機之間最常應用的組網形式。它是一個真正的開放系統，因為協議族的定義及其多種實現可以不用花錢或花很少的錢就可以公開地得到。它成為被稱作“全球互聯網”或“因特網(Internet)”的基礎，該廣域網（WA N）已包含超過1 0 0萬臺遍布世界各地的計算機。本章主要對T C P / I P協議族進行概述，其目的是為本書其余章節提供充分的背景知識。 TCP.IP協議 縮略語 ACK (ACKnowledgment) TCP首部中的確認標志 API (Application Programming Interface) 應用編程接口 ARP (Address Resolution Protocol) 地址解析協議 ARPANET(Defense Advanced Research Project Agency NETwork) (美國)國防部遠景研究規劃局 AS (Autonomous System) 自治系統 ASCII (American Standard Code for Information Interchange) 美國信息交換標準碼 ASN.1 (Abstract Syntax Notation One) 抽象語法記法1 BER (Basic Encoding Rule) 基本編碼規則 BGP (Border Gateway Protocol) 邊界網關協議 BIND (Berkeley Internet Name Domain) 伯克利I n t e r n e t域名 BOOTP (BOOTstrap Protocol) 引導程序協議 BPF (BSD Packet Filter) BSD 分組過濾器 CIDR (Classless InterDomain Routing) 無類型域間選路 CIX (Commercial Internet Exchange) 商業互聯網交換 CLNP (ConnectionLess Network Protocol) 無連接網絡協議 CRC (Cyclic Redundancy Check) 循環冗余檢驗 CSLIP (Compressed SLIP) 壓縮的S L I P CSMA (Carrier Sense Multiple Access) 載波偵聽多路存取 DCE (Data Circuit-terminating Equipment) 數據電路端接設備 DDN (Defense Data Network) 國防數據網 DF (Don’t Fragment) IP首部中的不分片標志 DHCP (Dynamic Host Configuration Protocol) 動態主機配置協議 DLPI (Data Link Provider Interface) 數據鏈路提供者接口 DNS (Domain Name System) 域名系統 DSAP (Destination Service Access Point) 目的服務訪問點 DSLAM (DSL Access Multiplexer) 數字用戶線接入復用器 DSSS (Direct Sequence Spread Spectrum) 直接序列擴頻 DTS (Distributed Time Service) 分布式時間服務 DVMRP (Distance Vector Multicast Routing Protocol) 距離向量多播選路協議 EBONE (European IP BackbONE) 歐洲I P主干網 EOL (End of Option List) 選項清單結束 EGP (External Gateway Protocol) 外部網關協議 EIA (Electronic Industries Association) 美國電子工業協會 FCS (Frame Check Sequence) 幀檢驗序列 FDDI (Fiber Distributed Data Interface) 光纖分布式數據接口 FIFO (First In, First Out) 先進先出 FIN (FINish) TCP首部中的結束標志 FQDN (Full Qualified Domain Name) 完全合格的域名 FTP (File Transfer Protocol) 文件傳送協議 HDLC (High-level Data Link Control) 高級數據鏈路控制 HELLO 選路協議 IAB (Internet Architecture Board) Internet體系結構委員會 IANA (Internet Assigned Numbers Authority) Internet號分配機構 ICMP (Internet Control Message Protocol) Internet控制報文協議 IDRP (InterDomain Routing Protocol) 域間選路協議 IEEE (Institute of Electrical and Electronics Engineering) （美國）電氣與電子工程師協會 IEN (Internet Experiment Notes) 互聯網試驗注釋 IESG (Internet Engineering Steering Group) Internet工程指導小組 IETF (Internet Engineering Task Force) Internet工程專門小組 IGMP (Internet Group Management Protocol) Internet組管理協議 IGP (Interior Gateway Protocol) 內部網關協議 IMAP (Internet Message Access Protocol) Internet報文存取協議 IP (Internet Protocol) 網際協議 I RTF (Internet Research Task Force) Internet研究專門小組 IS-IS (Intermediate System to Intermediate System Protocol) 中間系統到中間系統協議 ISN (Initial Sequence Number) 初始序號 ISO (International Organization for Standardization) 國際標準化組織 ISOC (Internet SOCiety) Internet協會 LAN (Local Area Network) 局域網 LBX (Low Bandwidth X) 低帶寬X LCP (Link Control Protocol) 鏈路控制協議 LFN (Long Fat Net) 長肥網絡 LIFO (Last In, First Out) 后進先出 LLC (Logical Link Control) 邏輯鏈路控制 LSRR (Loose Source and Record Route) 寬松的源站及記錄路由 MBONE (Multicast Backbone On the InterNEt) Internet上的多播主干網 MIB (Management Information Base) 管理信息庫 MILNET (MILitary NETwork) 軍用網 MIME (Multipurpose Internet Mail Extensions) 通用I n t e r n e t郵件擴充 MSL (Maximum Segment Lifetime) 報文段最大生存時間 MSS (Maximum Segment Size) 最大報文段長度 M TA (Message Transfer Agent) 報文傳送代理 MTU (Maximum Transmission Unit) 最大傳輸單元 NCP (Network Control Protocol) 網絡控制協議 NFS (Network File System) 網絡文件系統 NIC (Network Information Center) 網絡信息中心 NIT (Network Interface Tap) 網絡接口栓（S u n公司的一個程序） NNTP (Network News Transfer Protocol) 網絡新聞傳送協議 NOAO (National Optical Astronomy Observatories) 國家光學天文臺 NOP (No Operation) 無操作 NSFNET (National Science Foundation NETwork) 國家科學基金網絡 NSI (NASA Science Internet) （美國）國家宇航局I n t e r n e t NTP (Network Time Protocol) 網絡時間協議 NVT (Network Virtual Terminal) 網絡虛擬終端 OSF (Open Software Foudation) 開放軟件基金 OSI (Open Systems Interconnection) 開放系統互連 OSPF (Open Shortest Path First) 開放最短通路優先 PAWS (Protection Against Wrapped Sequence number) 防止回繞的序號 PDU (Protocol Data Unit) 協議數據單元 POSIX (Portable Operating System Interface) 可移植操作系統接口 PPP (Point-to-Point Protocol) 點對點協議 PSH (PuSH) TCP首部中的急迫標志 RARP (Reverse Address Resolution Protocol) 逆地址解析協議 RFC (Request For Comments) Internet的文檔，其中的少部分成為標準文檔 RIP (Routing Information Protocol) 路由信息協議 RPC (Remote Procedure Call) 遠程過程調用 RR (Resource Record) 資源記錄 RST (ReSeT) TCP首部中的復位標志 RTO (Retransmission Time Out) 重傳超時 RTT (Round-Trip Time) 往返時間 SACK (Selective ACKnowledgment) 有選擇的確認 SLIP (Serial Line Internet Protocol) 串行線路I n t e r n e t協議 SMI (Structure of Management Information) 管理信息結構 SMTP (Simple Mail Transfer Protocol) 簡單郵件傳送協議 SNMP (Simple Network Management Protocol) 簡單網絡管理協議 SSAP (Source Service Access Point) 源服務訪問點 SSRR (Strict Source and Record Route) 嚴格的源站及記錄路由 SWS (Silly Window Syndrome) 糊涂窗口綜合癥 SYN (SYNchronous) TCP首部中的同步序號標志 TCP (Transmission Control Protocol) 傳輸控制協議 TFTP (Trivial File Transfer Protocol) 簡單文件傳送協議 TLI (Transport Layer Interface) 運輸層接口 TTL (Ti m e - To-Live) 生存時間或壽命 TUBA (TCP and UDP with Bigger Addresses) 具有更長地址的T C P和U D P Telnet 遠程終端協議 UA (User Agent) 用戶代理 UDP (User Datagram Protocol) 用戶數據報協議 URG (URGent) TCP首部中的緊急指針標志 UTC (Coordinated Universal Time) 協調的統一時間 UUCP (Unix-to-Unix CoPy) Unix到U n i x的復制 WAN (Wide Area Network) 廣域網 WWW (World Wide Web) 萬維網 XDR (eXternal Data Representation) 外部數據表示 XID (transaction ID) 事務標識符 XTI (X/Open Transport Layer Interface) X/ O p e n運輸層接口
上傳時間： 2013-11-13
上傳用戶：tdyoung
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標簽： PicoBlaze Create Master Xilinx
上傳時間： 2013-11-12
上傳用戶：大三三
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP Algorithms with Xilinx FPGAs
上傳時間： 2013-10-21
上傳用戶：huql11633
The fundamental problem of communication is that of reproducing at one point either exactly or approximately a message selected at another point. Frequently the messages have meaning; that is they refer to or are correlated according to some system with certain physical or conceptual entities.
標簽： 通信
上傳時間： 2013-11-11
上傳用戶：xy@1314
PCB LAYOUT 術語解釋(TERMS)1. COMPONENT SIDE(零件面、正面)︰大多數零件放置之面。2. SOLDER SIDE(焊錫面、反面)。3. SOLDER MASK(止焊膜面)︰通常指Solder Mask Open 之意。4. TOP PAD︰在零件面上所設計之零件腳PAD，不管是否鑽孔、電鍍。5. BOTTOM PAD：在銲錫面上所設計之零件腳PAD，不管是否鑽孔、電鍍。6. POSITIVE LAYER：單、雙層板之各層線路；多層板之上、下兩層線路及內層走線皆屬之。7. NEGATIVE LAYER：通常指多層板之電源層。8. INNER PAD：多層板之POSITIVE LAYER 內層PAD。9. ANTI-PAD：多層板之NEGATIVE LAYER 上所使用之絕緣範圍，不與零件腳相接。10. THERMAL PAD：多層板內NEGATIVE LAYER 上必須零件腳時所使用之PAD，一般稱為散熱孔或導通孔。11. PAD (銲墊)：除了SMD PAD 外，其他PAD 之TOP PAD、BOTTOM PAD 及INNER PAD 之形狀大小皆應相同。12. Moat : 不同信號的 Power& GND plane 之間的分隔線13. Grid : 佈線時的走線格點2. Test Point : ATE 測試點供工廠ICT 測試治具使用ICT 測試點 LAYOUT 注意事項:PCB 的每條TRACE 都要有一個作為測試用之TEST PAD(測試點)，其原則如下：1. 一般測試點大小均為30-35mil，元件分布較密時，測試點最小可至30mil.測試點與元件PAD 的距離最小為40mil。2. 測試點與測試點間的間距最小為50-75mil，一般使用75mil。密度高時可使用50mil,3. 測試點必須均勻分佈於PCB 上，避免測試時造成板面受力不均。4. 多層板必須透過貫穿孔(VIA)將測試點留於錫爐著錫面上(Solder Side)。5. 測試點必需放至於Bottom Layer6. 輸出test point report(.asc 檔案powerpcb v3.5)供廠商分析可測率7. 測試點設置處:Setuppadsstacks
上傳時間： 2013-11-17
上傳用戶：cjf0304
Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which includes the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
上傳時間： 2013-11-16
上傳用戶：萍水相逢
LAYOUT REPORT .............. 1 目錄.................. 1 1. PCB LAYOUT 術語解釋(TERMS)......... 2 2. Test Point : ATE 測試點供工廠ICT 測試治具使用............ 2 3. 基準點 (光學點) -for SMD:........... 4 4. 標記 (LABEL ING)......... 5 5. VIA HOLE PAD................. 5 6. PCB Layer 排列方式...... 5 7.零件佈置注意事項 (PLACEMENT NOTES)............... 5 8. PCB LAYOUT 設計............ 6 9. Transmission Line ( 傳輸線 )..... 8 10.General Guidelines – 跨Plane.. 8 11. General Guidelines – 繞線....... 9 12. General Guidelines – Damping Resistor. 10 13. General Guidelines - RJ45 to Transformer................. 10 14. Clock Routing Guideline........... 12 15. OSC & CRYSTAL Guideline........... 12 16. CPU
上傳時間： 2013-10-29
上傳用戶：1234xhb
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control algorithms such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
