手把手教你學(xué)CPLD/FPGA與單片機(jī)聯(lián)合設(shè)計(jì)(前3章) 作者:周興華;出版社: 北京航空航天大學(xué)出版社 內(nèi)容簡(jiǎn)介:本書(shū)以實(shí)踐(實(shí)驗(yàn))為主線,以生動(dòng)短小的實(shí)例為靈魂,穿插介紹了Verilog HDL語(yǔ)言的語(yǔ)法及Altera公司的EPM7128S(或Atmel公司的ATFl508A5)設(shè)計(jì)開(kāi)發(fā)編程。理論與實(shí)踐緊密結(jié)合,由淺入深、循序漸進(jìn)地引導(dǎo)讀者進(jìn)行學(xué)習(xí)、實(shí)驗(yàn),這樣讀者學(xué)得進(jìn)、記得牢,不會(huì)產(chǎn)生畏難情緒,無(wú)形之中就掌握了 CPLD/FPGA的聯(lián)合設(shè)計(jì)。
標(biāo)簽: CPLD FPGA 手把手 單片機(jī)
上傳時(shí)間: 2013-10-20
上傳用戶(hù):xjz632
FPGA設(shè)計(jì)管腳分配注意點(diǎn)
上傳時(shí)間: 2014-12-28
上傳用戶(hù):franktu
EP2C5和EP2C8的FPGA開(kāi)發(fā)板原理圖,EP2C5_EP2C8 FPGA開(kāi)發(fā)板電路圖。
標(biāo)簽: EP FPGA 開(kāi)發(fā)板 電路圖
上傳時(shí)間: 2014-01-13
上傳用戶(hù):劉江林1420
altera FPGA/CPLD高級(jí)篇(VHDL源代碼)
標(biāo)簽: altera FPGA CPLD VHDL
上傳時(shí)間: 2014-12-28
上傳用戶(hù):15527161163
寫(xiě)給小白們的FPGA入門(mén)設(shè)計(jì)實(shí)驗(yàn): 1. 寫(xiě)在前面的話 2 2. Lab 1 : LCD1602 字符顯示設(shè)計(jì) 3 2.1. 摘要 2.2. 內(nèi)容 2.3. 程序 2.4. 結(jié)果(問(wèn)題,解決,體會(huì)) 3. Lab 2 : 4 位減法、加法器設(shè)計(jì) 3.1. 摘要 3.2. 內(nèi)容 3.3. 程序 3.4. 結(jié)果(問(wèn)題,解決,體會(huì)) 4. Lab 3 :三位二進(jìn)制乘法器設(shè)計(jì) 4.1. 摘要 4.2. 內(nèi)容 4.3. 程序 4.4. 結(jié)果(問(wèn)題,解決,體會(huì)) 5. Lab 4 :序列檢測(cè)器設(shè)計(jì) 6. Lab 5 :變模計(jì)數(shù)器設(shè)計(jì)
標(biāo)簽: FPGA 設(shè)計(jì)實(shí)驗(yàn)
上傳時(shí)間: 2013-11-05
上傳用戶(hù):silenthink
描述了基于FPGA的FIR濾波器設(shè)計(jì)。根據(jù)FIR的原理及嚴(yán)格線性相位濾波器具有偶對(duì)稱(chēng)的性質(zhì)給出了FIR濾波器的4種結(jié)構(gòu),即直接乘加結(jié)構(gòu)、乘法器復(fù)用結(jié)構(gòu)、乘累加結(jié)構(gòu)、DA算法。在本文中給出上述幾種算法的結(jié)構(gòu)框圖,并通過(guò)FPGA編程實(shí)現(xiàn)上述幾種算法,并給出所用的資源來(lái)比較各種算法的優(yōu)劣。
標(biāo)簽: FPGA FIR 濾波器 對(duì)比
上傳時(shí)間: 2013-12-09
上傳用戶(hù):lvzhr
本資料是關(guān)于基于Quartus II FPGA/CPLD數(shù)字系統(tǒng)設(shè)計(jì)實(shí)例(VHDL源代碼文件),需要的可以自己下載。
標(biāo)簽: Quartus FPGA CPLD VHDL
上傳時(shí)間: 2013-10-13
上傳用戶(hù):caiiicc
基于Altera公司FPGA芯片EP2C8Q208,嵌入MC8051 IP Core,用C語(yǔ)言對(duì)MC8051 IP Core進(jìn)行編程,以其作為控制核心,實(shí)現(xiàn)系統(tǒng)控制。在FPGA芯片中,利用Verilog HDL語(yǔ)言進(jìn)行編程,設(shè)計(jì)了以MC8051 IP Core為核心的控制模塊、計(jì)數(shù)模塊、鎖存模塊和LCD顯示模塊等幾部分,實(shí)現(xiàn)了頻率的自動(dòng)測(cè)量,測(cè)量范圍為0.1Hz~50MHz,測(cè)量誤差0.01%。并實(shí)現(xiàn)測(cè)頻率、周期、占空比等功能。
上傳時(shí)間: 2013-10-14
上傳用戶(hù):1214209695
FPGA-CPLD芯片設(shè)置方法
上傳時(shí)間: 2013-10-28
上傳用戶(hù):whymatalab2
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽: FPGA 安全系統(tǒng)
上傳時(shí)間: 2013-11-05
上傳用戶(hù):維子哥哥
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