This paper examines the asymptotic (large sample) performance
of a family of non-data aided feedforward (NDA FF) nonlinear
least-squares (NLS) type carrier frequency estimators for burst-mode
phase shift keying (PSK) modulations transmitted through AWGN and
flat Ricean-fading channels. The asymptotic performance of these estimators
is established in closed-form expression and compared with the
modified Cram`er-Rao bound (MCRB). A best linear unbiased estimator
(BLUE), which exhibits the lowest asymptotic variance within the family
of NDA FF NLS-type estimators, is also proposed.
In recent years large scientific interest has been
devoted to joint data decoding and parameter estimation
techniques. In this paper, iterative turbo decoding joint
to channel frequency and phase estimation is proposed.
The phase and frequency estimator is embedded into the
structure of the turbo decoder itself, taking into consideration
both turbo interleaving and puncturing. Results
show that the proposed technique outperforms conventional
approaches both in terms of detection capabilities and
implementation complexity.
Carrier-phase synchronization can be approached in a
general manner by estimating the multiplicative distortion (MD) to which
a baseband received signal in an RF or coherent optical transmission
system is subjected. This paper presents a unified modeling and
estimation of the MD in finite-alphabet digital communication systems. A
simple form of MD is the camer phase exp GO) which has to be estimated
and compensated for in a coherent receiver. A more general case with
fading must, however, allow for amplitude as well as phase variations of
the MD.
We assume a state-variable model for the MD and generally obtain a
nonlinear estimation problem with additional randomly-varying system
parameters such as received signal power, frequency offset, and Doppler
spread. An extended Kalman filter is then applied as a near-optimal
solution to the adaptive MD and channel parameter estimation problem.
Examples are given to show the use and some advantages of this scheme.
This program simulates the bit-error-rate (BER) performance of OSTBC
with L=4 antennas over the frequency flat Rayleigh block fading channel
The code is developed for real orthogonal design, code rate 1/2
modulation- 16 QAM with gray coding resulting in 2 bits/sec/Hz.
This project aim was to build wireless software modem for data communication
between two computers using an acoustic interface in the voice frequency range (20Hz–
20,000Hz). The transmitting antenna is a speaker (frequency response of: 90Hz –
20,000Hz) and the receiving antenna is a microphone (frequency response of: 100Hz –
16,000Hz). The test files used as information files were text files.
This goal was attained both in an incoherent scheme and in a coherent scheme.
Build under Matlab code, our modem uses OFDM (orthogonal frequency division
multiplexing) modulation, synchronization by LMS sequence, channel estimation (no
equalizer) via pilot tones. The symbols are either PSK or ASK for a constellation size of
2 or 4. To optimize the probability of error, these symbols were mapped using Gray
mapping.
Report
A digital fi‘equeney meter designed with FPGA development software Q-~us 11 is introduced．The 1 Hz—l MHz input measured pulse signals of the digital ii‘equency meter can be used for measuring frequency，period，pulse width and duty ratio，etc．The test results stably display O71 3 seven—segment numeric tubes，and the measuring ranges may be switched over automatically．The measuring error is equal to or less than 0．1％．
DFT(Discrete Fourier Transformation)是數字信號分析與處理如圖形、語音及圖像等領域的重要變換工具，直接計算DFT的計算量與變換區間長度N的平方成正比。當N較大時，因計算量太大，直接用DFT算法進行譜分析和信號的實時處理是不切實際的。快速傅立葉變換(Fast Fourier Transformation，簡稱FFT)使DFT運算效率提高1～2個數量級。其原因是當N較大時，對DFT進行了基4和基2分解運算。FFT算法除了必需的數據存儲器ram和旋轉因子rom外，仍需較復雜的運算和控制電路單元，即使現在,實現長點數的FFT仍然是很困難。本文提出的FFT實現算法是基于FPGA之上的，算法完成對一個序列的FFT計算，完全由脈沖觸發，外部只輸入一脈沖頭和輸入數據，便可以得到該脈沖頭作為起始標志的N點FFT輸出結果。由于使用了雙ram，該算法是流型(Pipelined)的，可以連續計算N點復數輸入FFT，即輸入可以是分段N點連續復數數據流。采用DIF(Decimation In Frequency)-FFT和DIT(Decimation In Time)-FFT對于算法本身來說是無關緊要的，因為兩種情況下只是存儲器的讀寫地址有所變動而已，不影響算法的結構和流程，也不會對算法復雜度有何影響。
This example demonstrates how the C8051F06x SMBus interface can communicate
// with a 256 byte I2C Serial EEPROM (Microchip 24LC02B).
// - Interrupt-driven SMBus implementation
// - Only master states defined (no slave or arbitration)
// - Timer4 used by SMBus for SCL low timeout detection
// - SCL frequency defined by <SMB_FREQUENCY> constant
