頻率合成技術在現代電子技術中具有重要的地位。在通信、雷達和導航等設備中，它可以作為干擾信號發生器；在測試設備中，可作為標準信號源，因此頻率合成器被人們稱為許多電子系統的“心臟”。直接數字頻率合成（DDS——Digital Direct frequency Synthesis）技術是一種全新的頻率合成方法，是頻率合成技術的一次革命。本文主要分析了DDS的基本原理及其輸出頻譜特點，并采用VHDL語言在FPGA上實現。對于DDS的輸出頻譜，一個較大的缺點是：輸出雜散較大。針對這一缺點本文使用了兩個方法加以解決。首先是壓縮ROM查找表，
上傳時間： 2017-09-28
上傳用戶：大三三
OFDM(Orthogonal frequency Division Multiplexing)即正交頻分復用技術，實際上OFDM是多載波調制的一種。其主要思想是：將信道分成若干正交子信道，將高速數據信號轉換成并行的低速子數據流，調制到在每個子信道上進行傳輸。正交信號可以通過在接收端采用相關技術來分開，這樣可以減少子信道之間的相互干擾 ICI 。每個子信道上的信號帶寬小于信道的相關帶寬，因此每個子信道上的可以看成平坦性衰落，從而可以消除符號間干擾。而且由于每個子信道的帶寬僅僅是原信道帶寬的一小部分，信道均衡變得相對容易。
標簽： OFDM
上傳時間： 2015-02-17
上傳用戶：hongyun288
FILE NAME: dc_motor.c CHIP TYPE: ATMEGA16 CLOCK frequency: 8MHZ IDE: VSMStudio COMPILER: AVR-GCC
標簽： PWM
上傳時間： 2015-03-01
上傳用戶：abilibili
有多徑信道、多普勒頻移，瑞利、RICE(萊斯)信道等仿真，QPSK調制和解調等，交織編碼。程序經過本人測試，絕對可用，并附上本人測試說明和仿真圖像結果-I collected information on 2, how-path channel, Doppler frequency shift, Rayleigh, RICE (Rice) channel, such as simulation, QPSK modulation and demodulation, etc., Interleaved Coded. After I tested the procedure is absolutely available, along with my test images and simulation results indicate.
上傳時間： 2015-06-16
上傳用戶：whtiger
自適應軟頻率復用技術在長期演進中上行上的應用，主要是如何解決小區邊緣干擾問題。對小區邊緣干擾提出了自適應軟頻率復用算法
標簽： Interference Inter-cell frequency Adaptive Reuse Soft for
上傳時間： 2016-05-09
上傳用戶：cococo
msp430The LDC1312 and LDC1314 are 2- and 4-channel, 1? Easy-to-use – minimal configuration required 12-bit inductance to digital converters (LDCs) for ? Measure up to 4 sensors with one IC inductive sensing solutions. With multiple channels ? Multiple channels support environmental and and support for remote sensing, the LDC1312 and aging compensation LDC1314 enable the performance and reliability benefits of inductive sensing to be realized at minimal? Multi-channel remote sensing provides lowest cost and power. The products are easy to use, onlysystem cost requiring that the sensor frequency be within 1 kHz ? Pin-compatible medium and high-resolution and 10 MHz to begin sensing. The wide 1 kHz to 10 options MHz sensor frequency range also enables use of very small PCB coils, further reducing sensing– LDC1312/4: 2/4-ch 12-bit LDC solution cost and size.– LDC1612/4: 2/4-ch 28
上傳時間： 2016-07-22
上傳用戶：tongmoonsky
The AP2406 is a 1.5Mhz constant frequency, slope compensated current mode PWM step-down converter. The device integrates a main switch and a synchronous rectifier for high efficiency without an external Schottky diode. It is ideal for powering portable equipment that runs from a single cell lithium-Ion (Li+) battery. The AP2406 can supply 600mA of load current from a 2.5V to 5.5V input voltage. The output voltage can be regulated as low as 0.6V. The AP2406 can also run at 100% duty cycle for low dropout operation, extending battery life in portable system. Idle mode operation at light loads provides very low output ripple voltage for noise sensitive applications. The AP2406 is offered in a low profile (1mm) 5-pin, thin SOT package, and is available in an adjustable version and fixed output voltage of 1.2V, 1.5V and 1.8V
上傳時間： 2017-02-23
上傳用戶：w124141
ADI公司的引用筆記，講解了鎖相環在通信接收機和發射機的應用
標簽： transmitters frequency receivers high pll for and
上傳時間： 2017-03-13
上傳用戶：rfzhangyicheng
1.高頻率pll 設計論文 2.描述相應的設計思想
標簽： Synthesizer frequency Charge Pump GHz PLL
上傳時間： 2017-05-02
上傳用戶：橡樹園林
The 4.0 kbit/s speech codec described in this paper is based on a frequency Domain Interpolative (FDI) coding technique, which belongs to the class of prototype waveform Interpolation (PWI) coding techniques. The codec also has an integrated voice activity detector (VAD) and a noise reduction capability. The input signal is subjected to LPC analysis and the prediction residual is separated into a slowly evolving waveform (SEW) and a rapidly evolving waveform (REW) components. The SEW magnitude component is quantized using a hierarchical predictive vector quantization approach. The REW magnitude is quantized using a gain and a sub-band based shape. SEW and REW phases are derived at the decoder using a phase model, based on a transmitted measure of voice periodicity. The spectral (LSP) parameters are quantized using a combination of scalar and vector quantizers. The 4.0 kbits/s coder has an algorithmic delay of 60 ms and an estimated floating point complexity of 21.5 MIPS. The performance of this coder has been evaluated using in-house MOS tests under various conditions such as background noise. channel errors, self-tandem. and DTX mode of operation, and has been shown to be statistically equivalent to ITU-T (3.729 8 kbps codec across all conditions tested.
標簽： frequency-domain interpolation performance Design kbit_s speech coder based and of
上傳時間： 2018-04-08
上傳用戶：kilohorse
