A sample program to demonstrate the usage of signal handling in linux C programing language.
標簽： demonstrate programing handling language
上傳時間： 2013-12-19
上傳用戶：zhouli
complete information about unix and handling database
標簽： information complete handling database
上傳時間： 2017-04-16
上傳用戶：zhaoq123
grievance handling system
上傳時間： 2013-12-13
上傳用戶：wl9454
simple ATmega8 source codes for timer handling
標簽： handling ATmega8 simple source
上傳時間： 2014-06-20
上傳用戶：WMC_geophy
simple atmega8 codes for sw and light handling
標簽： handling atmega8 simple codes
上傳時間： 2013-12-16
上傳用戶：1109003457
handling IRPs: What Every Driver Writer Needs to Know
標簽： handling Driver Writer Every
上傳時間： 2014-01-22
上傳用戶：541657925
handling Request Parameters with Form Beans
標簽： Parameters handling Request Beans
上傳時間： 2013-12-29
上傳用戶：LouieWu
介紹基于ISA總線與KH-9300的數據采集板卡的設置，詳細說明8254定時計數器及8259中斷控制器的結構特點、工作方式、控制字等，探討中斷類型、中斷處理程序、中斷矢量表及其填寫。重點講述使用TorboC編寫中斷服務程序的方法，應注意的主要問題及程序測試的結果。 Abstract: The settings of KH-9300 data acquisition board based on the ISA bus is introduced,the structural characteristics,working methods,control characters of the timing counter 8254 and interruptioncontroller 8259 are explained in detail.The interruption type,interrupt handling programs,interruption vector table and its filling also are discussed.Further,great emphasis is put on the method of interrupt service program compiled by Torbo C,the main issues that should be noted,and the results of program testing.
上傳時間： 2013-11-14
上傳用戶：qq527891923
This application note shows how to write an Inter Integrated Circuit bus driver (I²C) for the Philips P90CL301micro-controller.It is not only an example of writing a driver, but it also includes a set of application interface software routines toquickly implement a complete I²C multi-master system application.For specific applications the user will have to make minimal changes in the driver program. Using the drivermeans linking modules to your application software and including a header-file into the application sourceprograms. A small example program of how to use the driver is listed.The driver supports i.a. polled or interrupt driven message handling, slave message transfers and multi-mastersystem applications. Furthermore, it is made suitable for use in conjunction with real time operating systems, likepSOS+.
上傳時間： 2013-11-23
上傳用戶：weixiao99
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
