Features• Complete DTMF Receiver• Low power consumption• internal gain setting amplifier• Adjustable guard time• Central office quality• Power-down mode• Inhibit mode• Backward compatible withMT8870C/MT8870C-1Applications• Receiver system for British Telecom (BT) orCEPT Spec (MT8870D-1)• Paging systems• Repeater systems/mobile radio• Credit card systems• Remote control• Personal computers• Telephone answering machine
上傳時間： 2013-11-20
上傳用戶：mpquest
C51使用手冊 .pdf 第二節內存區域(Memory Areas)1. Pragram Area由Code 說明可有多達64kBytes 的程序存儲器2. internal Data Memory:內部數據存儲器可用以下關鍵字說明data 直接尋址區為內部RAM 的低128 字節00H 7FHidata 間接尋址區 包括整個內部RAM 區00H FFHbdata 可位尋址區 20H 2FH3. External Data Memory外部RAM 視使用情況可由以下關鍵字標識xdata 可指定多達64KB 的外部直接尋址區地址范圍0000H 0FFFFHpdata 能訪問1 頁(25bBytes)的外部RAM 主要用于緊湊模式(Compact Model)4. Speciac Function Register Memory
上傳時間： 2013-11-19
上傳用戶：busterman
The CAT823, CAT824, and CAT825 provide basic reset and monitoring functions for the electronic systems. Each device monitors the system voltage and maintains a reset output until that voltage reaches the device’s specified trip value and then maintains the reset output active condition until the device’s internal timer, after a minimum timer of 140ms; toallow the systems power supply to stabilize.
上傳時間： 2014-11-18
上傳用戶：BOBOniu
The XL6003 regulator is fixed frequency PWM Boost (step-up) DC/DC converter, capable ofdriving 1050mA load current with excellent line and load regulation. The regulator is simple to use because it includes internal frequency compensation and a fixed-frequency oscillator so that it requires a minimum number of external components to work. The XL6003 could directly drive 5~10 3W LED units at VIN=12V.
上傳時間： 2013-11-07
上傳用戶：xy@1314
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上傳時間： 2014-11-22
上傳用戶：xcy122677
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
上傳時間： 2013-10-13
上傳用戶：bakdesec
Although Stellaris microcontrollers have generous internal SRAM capabilities, certain applicationsmay have data storage requirements that exceed the 8 KB limit of the Stellaris LM3S8xx seriesdevices. Since microcontrollers do not have an external parallel data-bus, serial memory optionsmust be considered. Until recently, the ubiquitous serial EEPROM/flash device was the only serialmemory solution. The major limitations of EEPROM and flash technology are slow write speed, slowerase times, and limited write/erase endurance.Recently, serial SRAM devices have become available as a solution for high-speed dataapplications. The N256S08xxHDA series of devices, from AMI Semiconductor, offer 32 K x 8 bits oflow-power data storage, a fast Serial Peripheral Interface (SPI) serial bus, and unlimited write cycles.The parts are available in 8-pin SOIC and compact TSSOP packages.
上傳時間： 2013-10-14
上傳用戶：cxl274287265
The main oscillator allows either a crystal or single-ended input clock signal. Cost-sensitiveapplications typically use an external crystal with the on-chip oscillator circuit since it is the mostcost-effective solution. It is also possible to use the internal oscillator to clock the device after theboot process has completed.
標簽： Stellaris Clocking Options for
上傳時間： 2013-10-14
上傳用戶：pol123
本文檔將深入介紹內部時鐘源模塊（internal ClockSource， ICS），該模塊可以在部分HCS08 系列微控制器中找到。對HCS08 MCU 來說， ICS 模塊不但是一個非常靈活的時鐘源，而且對于該系列中更小、更低成本的MCU來說非常經濟。ICS 包括鎖頻環、內部時鐘參考、外部振蕩器和時鐘選擇子模塊。這些子模塊組合可以提供多種時鐘模式和頻率，以滿足任何應用的需要。本應用筆記詳細描述ICS 的7 種工作模式、ICS 模塊與其他HCS08 MCU 的內部時鐘發生器（internal ClockGenerator， ICG）模塊作比較、ICS 模塊從不同低功耗模式下恢復的特性及內部時鐘參考的校準方法。
上傳時間： 2013-11-08
上傳用戶：zhuoying119
The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標簽： synchronous Emulating serial
上傳時間： 2014-01-31
上傳用戶：z1191176801
