The data plane of the reference design consists of a configurable multi-channel XBERT modulethat generates and checks high-speed serial data transmitted and received by the MGTs. Eachchannel in the XBERT module consists of two MGTs (MGTA and MGTB), which physicallyoccupy one MGT tile in the Virtex-4 FPGA. Each MGT has its own pattern checker, but bothMGTs in a channel share the same pattern generator. Each channel can load a differentpattern. The MGT serial rate depends on the reference clock frequency and the internal PMAdivider settings. The reference design can be scaled anywhere from one channel (two MGTs)to twelve channels (twenty-four MGTs).
標(biāo)簽： RocketIO Virtex XAPP 713
上傳時間： 2013-12-25
上傳用戶：jkhjkh1982
SL811開發(fā)資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
上傳時間： 2013-12-22
上傳用戶：a82531317
The ability to create groups of reports, and grant users access to reports by group. The ability to generate reports as PDF, XLS, HTML, and CSV files. The ability to generate bar, pie and xy charts for inclusion in reports. The ability to schedule and email PDF, XLS, and CSV reports. The ability to define reusable report parameters. Available parameter types include Date, Text, and Query Parameters. The ability to create multiple DataSources for use in generating reports. Support for JNDI DataSources and internal connection pooling via Commons-DBCP is included. The ability to upload and hot deploy new reports. Web based administration of users, groups, reports, parameters, and datasources. Cross platform database support via Hibernate based persistence layer. Available in a preconfigured bundle with Apache Tomcat.
標(biāo)簽： ability reports The to
上傳時間： 2014-01-14
上傳用戶：franktu
This program prints the C8051F124 die temperature out the hardware UART at 115200bps. This example uses the internal 24.5MHz oscillator multiplied by 2 using the on-chip PLL (SYSCLK = 49MHz).
標(biāo)簽： This temperature C8051F124 the
上傳時間： 2014-01-12
上傳用戶：Avoid98
This a very simple Yee algorithm 3D FDTD code in C implementing the free space form of Maxwell s equations on a Cartesian grid. There are no internal materials or geometry. The code as delivered simulates an idealized rectangular waveguide by treating the interior of the mesh as free space/air and enforcing PEC (Perfect Electric Conductor) conditions on the faces of the mesh.
標(biāo)簽： implementing algorithm Maxwell simple
上傳時間： 2015-05-14
上傳用戶：水中浮云
十部經(jīng)典算法合集 .chm Fundamentals of Data Structures by Ellis Horowitz and Sartaj Sahni PREFACE CHAPTER 1: INTRODUCTION CHAPTER 2: ARRAYS CHAPTER 3: STACKS AND QUEUES CHAPTER 4: LINKED LISTS CHAPTER 5: TREES CHAPTER 6: GRAPHS CHAPTER 7: internal SORTING CHAPTER 8: EXTERNAL SORTING CHAPTER 9: SYMBOL TABLES CHAPTER 10: FILES APPENDIX A: SPARKS APPENDIX B: ETHICAL CODE IN INFORMATION PROCESSING APPENDIX C: ALGORITHM INDEX BY CHAPTER
標(biāo)簽： Fundamentals Structures Horowitz PREFACE
上傳時間： 2015-05-19
上傳用戶：維子哥哥
These routines transmit and receive serial data using two general * I/O pins, in 8 bit, No parity, 1 stop bit format. They are useful * for performing serial I/O on 8051 derivatives not having an * internal UART, or for implementing a second serial channel.
標(biāo)簽： routines transmit receive general
上傳時間： 2015-05-22
上傳用戶：firstbyte
TIMER.ASM ********* [ milindhp@tifrvax.tifr.res.in ] Set Processor configuration word as = 0000 0000 1010 b. a] -MCLR tied to VDD (internally). b] Code protection off. c] WDT disabled. d] internal RC oscillator [4 MHZ].
標(biāo)簽： configuration Processor milindhp tifrvax
上傳時間： 2015-05-24
上傳用戶：wqxstar
Features • Compatible with MCS-51® Products • 8K Bytes of In-System Programmable (ISP) Flash Memory – Endurance: 1000 Write/Erase Cycles • 4.0V to 5.5V Operating Range • Fully Static Operation: 0 Hz to 33 MHz • Three-level Program Memory Lock • 256 x 8-bit internal RAM • 32 Programmable I/O Lines • Three 16-bit Timer/Counters • Eight Interrupt Sources • Full Duplex UART Serial Channel • Low-power Idle and Power-down Modes • Interrupt Recovery from Power-down Mode • Watchdog Timer • Dual Data Pointer • Power-off Flag
標(biāo)簽： 8226 Programmable Compatible In-System
上傳時間： 2015-06-27
上傳用戶：dianxin61
8051 monitor programm: - use external ram to run user program - use eeprom to save user program - provide single step debug, can read internal register and ram
標(biāo)簽： program user use external
上傳時間： 2015-07-11
上傳用戶：zhichenglu
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