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jftp-src-test

  • 本系統采用access+asp開發

    本系統采用access+asp開發,系統要求:windows9X+pws win2000(或更高)+IIS、IE 4.0以上及相關打印設備 2、處于安全考慮,建議安裝使用前,先修改數據庫路徑(默認為"tcadmin\tcmdb")及數據庫名稱,然后修改文件tcconn.asp相應路徑設置 3、本系統所有日期格式均為:yyyy-mm-dd,例如:2004-03-28.請按此格式輸入日期,否則日期數據拒絕存入數據庫 4、檔案輸出文件為word(*.doc)格式。由于個人配置及環境不一,所以輸出后建議用MS word稍作編輯 5、系統所有查找定位均支持模糊查找。例:輸入關鍵詞:"李",選擇條件按 "姓名" 查找,則記錄列表將顯示所有姓名中含有"李"字的教師記錄 6、教師業務檔案輸出時,建議先保存后編輯,以免給你造成不必要的麻煩 7、教師查詢頁面學院首頁指向:tcadmin/user_search.asp 8、教師業務檔案管理系統登陸頁面學院首頁調用:login.htm ,調用方法:首頁插入代碼:<iframe src="你的路徑/tcadmin/login.htm" scrolling="no" frameborder="0"></ifram

    標簽: access asp

    上傳時間: 2014-01-01

    上傳用戶:wweqas

  • This Source.zip has three application code folders containing .java and .class files and two .jar fi

    This Source.zip has three application code folders containing .java and .class files and two .jar files as follows: 1. desktop-side_JXTA4JMS 2. mobile-side_JXTA4JMS 3. JMS Test Client 4. Listener.jar 5. JMSTestClient.jar We now explain execution steps, we followed, to run this JXTA4JMS application. Before we try we require Application softwares and need to configure JXTA relay and J2EE server.

    標簽: application containing and folders

    上傳時間: 2014-11-17

    上傳用戶:z1191176801

  • Universal Serial Bus Implementers Forum Full and Low Speed Electrical and Interoperability Compl

    Universal Serial Bus Implementers Forum Full and Low Speed Electrical and Interoperability Compliance Test Procedure

    標簽: Interoperability Implementers Electrical Universal

    上傳時間: 2015-11-18

    上傳用戶:cc1915

  • In addition to individual algorithm, Demonstration System is a "data structure" (C language version)

    In addition to individual algorithm, Demonstration System is a "data structure" (C language version) book algorithm corresponding to the code (CPP) and the test operating procedures (VC + +6.0 to the EXE). Through the system can demonstrate that the algorithm source code and operating results

    標簽: Demonstration individual algorithm structure

    上傳時間: 2013-12-24

    上傳用戶:change0329

  • Software Testing, Second Edition provides practical insight into the world of software testing and q

    Software Testing, Second Edition provides practical insight into the world of software testing and quality assurance. Learn how to find problems in any computer program, how to plan an effective test approach and how to tell when software is ready for release. Updated from the previous edition in 2000 to include a chapter that specifically deals with testing software for security bugs, the processes and techniques used throughout the book are timeless. This book is an excellent investment if you want to better understand what your Software Test team does or you want to write better software.

    標簽: practical Software provides software

    上傳時間: 2014-08-01

    上傳用戶:zhaiyanzhong

  • linux filesystem bootdisk-howto.This document describes how to design and build boot/root diskettes

    linux filesystem bootdisk-howto.This document describes how to design and build boot/root diskettes for Linux. These disks can be used as rescue disks or to test new system components. You should be reasonably familiar with system administration tasks before attempting to build a bootdisk. If you just want a rescue disk to have for emergencies,

    標簽: bootdisk-howto filesystem describes diskettes

    上傳時間: 2015-11-22

    上傳用戶:wanghui2438

  • This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDR

    This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec

    標簽: Development Startix2 tailored Altera

    上傳時間: 2014-01-19

    上傳用戶:chongcongying

  • 程序構架基于:運用JSP+Struts+JSTL技術的MVC架構

    程序構架基于:運用JSP+Struts+JSTL技術的MVC架構,數據庫采用SQL Server。 使用說明: 設置數據庫: 把/zefeng/database/zefenggb_Data數據庫文件,附加到SQL Server數據庫中,數據庫的用戶名和密碼設置成sa。 本程序源代碼在/zefeng/src/目錄下。

    標簽: Struts JSTL JSP MVC

    上傳時間: 2015-11-26

    上傳用戶:1051290259

  • 其中sound.c 用于錄音和回放。其中特別需要注意的是:1。目前聲卡似乎不能打開全雙工

    其中sound.c 用于錄音和回放。其中特別需要注意的是:1。目前聲卡似乎不能打開全雙工,所以如果fd = open("/dev/dsp", O_RDWR) ,則無法錄音和回放。只能分別設置RDONLY和WRONLY。即半雙工方式。否則,就是在錄音的時候可以聽見,但是無法回放。分析下來似乎是IIC總線中只分配了一個通道給聲卡,或者是只啟用了一個通道,所以無法錄音和放音同步進行。解決方法就是分別以RDONLY方式打開進行錄音和WRONLY方式打開進行放音。 Sound1.c用于將錄音保存在test.wav文件中,并利用cast test.wav > /dev/sound/dsp回放文件。此處需要注意的是,錄音頻率必須是44100才能正確回放。否則就會出現類似快放的效果。分析應該是cast方式利用了dsp的默認播放頻率44100,所以如果錄音的時候低于這個頻率,這放的時候就會快放。 此外,設置采樣率的時候必須設置成16bit,否則會提示出錯。原因尚不知道,估計是與聲卡有關。

    標簽: sound 回放 全雙工 聲卡

    上傳時間: 2013-12-31

    上傳用戶:cc1

  • verilog語言編寫的FPGA代碼。功能為pc機通過epp不斷寫數到sram中

    verilog語言編寫的FPGA代碼。功能為pc機通過epp不斷寫數到sram中,然后pc發送中斷信號打斷寫過程讀取sram中的數據。rar包中包含epp協議,模塊文件和測試文件(test)。

    標簽: verilog FPGA sram epp

    上傳時間: 2013-12-17

    上傳用戶:1966640071

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