ANALOG INPUT BANDWIDTH is a measure of the frequencyat which the reconstructed output fundamental drops3 dB below its low frequency value for a full scale input. Thetest is performed with fIN equal to 100 kHz plus integer multiplesof fCLK. The input frequency at which the output is −3dB relative to the low frequency input signal is the full powerbandwidth.APERTURE jitter is the variation in aperture delay fromsample to sample. Aperture jitter shows up as input noise.APERTURE DELAY See Sampling Delay.BOTTOM OFFSET is the difference between the input voltagethat just causes the output code to transition to the firstcode and the negative reference voltage. Bottom Offset isdefined as EOB = VZT–VRB, where VZT is the first code transitioninput voltage and VRB is the lower reference voltage.Note that this is different from the normal Zero Scale Error.CONVERSION LATENCY See PIPELINE DELAY.CONVERSION TIME is the time required for a completemeasurement by an analog-to-digital converter. Since theConversion Time does not include acquisition time, multiplexerset up time, or other elements of a complete conversioncycle, the conversion time may be less than theThroughput Time.DC COMMON-MODE ERROR is a specification which appliesto ADCs with differential inputs. It is the change in theoutput code that occurs when the analog voltages on the twoinputs are changed by an equal amount. It is usually expressed in LSBs.
上傳時間： 2013-11-12
上傳用戶：pans0ul
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2013-10-15
上傳用戶：busterman
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
上傳時間： 2014-01-24
上傳用戶：s363994250
Frequently, voltage reference stability and noise defi nemeasurement limits in instrumentation systems. In particular,reference noise often sets stable resolution limits.Reference voltages have decreased with the continuingdrop in system power supply voltages, making referencenoise increasingly important. The compressed signalprocessing range mandates a commensurate reductionin reference noise to maintain resolution. Noise ultimatelytranslates into quantization uncertainty in A to D converters,introducing jitter in applications such as scales, inertialnavigation systems, infrared thermography, DVMs andmedical imaging apparatus. A new low voltage reference,the LTC6655, has only 0.3ppm (775nV) noise at 2.5VOUT.Figure 1 lists salient specifi cations in tabular form. Accuracyand temperature coeffi cient are characteristic ofhigh grade, low voltage references. 0.1Hz to 10Hz noise,particularly noteworthy, is unequalled by any low voltageelectronic reference.
上傳時間： 2013-10-30
上傳用戶：wxhwjf
jitterbug是基于matlab的工具箱，允許對在不同的時域條件下的線性系統的二次性能指標計算。用這個工具箱，可以很容易看出系統對時延、jitter和數據丟失等的響應。
上傳時間： 2014-07-23
上傳用戶：qq521
NIST Net – A Linux-based Network Emulation Tool, It is a raw IP packet filter with many controllable channel parameters such as packet loss ratio, jitter, bandwidth variation, delay, and network buffer size. To simulate different network environments
標簽： controllable Linux-based Emulation Network
上傳時間： 2014-01-26
上傳用戶：xauthu
The TMS320VC5506/C5507/C5509A USB peripherals can be clocked from either the USB APLL or the USB DPLL. Since the APLL is inherently more noise tolerant and has less long-term jitter than the DPLL, it is recommended that you switch to it for any USB operations.
標簽： USB peripherals the clocked
上傳時間： 2014-01-01
上傳用戶：yuzsu
This book addresses two aspects of network operation quality; namely, resource management and fault management. Network operation quality is among the functions to be fulfilled in order to offer quality of service, QoS, to the end user. It is characterized by four parameters: – packet loss; – delay; – jitter, or the variation of delay over time; – availability. Resource management employs mechanisms that enable the first three parameters to be guaranteed or optimized. Fault management aims to ensure continuity of service.
標簽： Ethernet Networks MPLS and IP
上傳時間： 2020-05-27
上傳用戶：shancjb
設計高速電路必須考慮高速訊 號所引發的電磁干擾、阻抗匹配及串音等效應，所以訊號完整性 (signal integrity)將是考量設計電路優劣的一項重要指標，電路日異複雜必須仰賴可 靠的軟體來幫忙分析這些複雜的效應，才比較可能獲得高品質且可靠的設計， 因此熟悉軟體的使用也將是重要的研究項目之一。另外了解高速訊號所引發之 各種效應(反射、振鈴、干擾、地彈及串音等)及其克服方法也是研究高速電路 設計的重點之一。目前高速示波器的功能越來越多，使用上很複雜，必須事先 進修學習，否則無法全盤了解儀器之功能，因而無法有效發揮儀器的量測功能。 其次就是高速訊號量測與介面的一些測試規範也必須熟悉，像眼圖分析，探針 效應，抖動(jitter)測量規範及高速串列介面量測規範等實務技術，必須充分 了解研究學習，進而才可設計出優良之教學教材及教具。
標簽： 高速電路
上傳時間： 2021-11-02
上傳用戶：jiabin
CPCI_E標準規范 CompactPCI? Express SpecificationThe documents in this section may be useful for reference when reading the specification. The revision listed for each document is the latest revision at the time this specification was published. Newer revisions of these documents may exist, so refer to the newest revision. Many of these documents are referenced throughout this specification. Refer to the newest revision of the document unless a specific revision is referenced. ? PCI Express Base Specification 3.0. PCI Special Interest Group (PCI-SIG). ? PCI Express Card Electromechanical (CEM) Specification 3.0. PCI Special Interest Group (PCI-SIG). ? PCI Express to PCI/PCI-X Bridge Specification, Rev. 1.0. PCI Special Interest Group (PCI-SIG). ? PCI Express jitter White Paper. PCI Special Interest Group (PCI-SIG). ? PCIe Rj Dj BER White Paper. PCI Special Interest Group (PCI-SIG). ? PHY Electrical Test Specification for PCI Express Architecture. PCI Special Interest Group (PCI SIG). ? System Management Bus (SMBus) Specification, Version 2.0. Smart Battery System Implementer’
標簽： CPCIE
上傳時間： 2022-02-23
上傳用戶：
