本文針對由FPGA構成的高速數據采集系統數據處理能力弱的問題，提出FPGA與單片機實現數據串行通信的解決方
上傳時間： 2013-04-24
上傳用戶：cuicuicui
大量windows shell編程例子 - large windows shell programming examples
上傳時間： 2013-05-21
上傳用戶：15853744528
在國內Protel軟件一直大受歡迎，從DOS時代的Protel3.3(Autotrax 1.61)到現在具有EDA Client/Server （客戶/服務器）即C/S“框架”體系結構的Protel98，它始終是PCB設計和制造領域的大眾化工具軟件，成為電子設計工作者們的首選。 在規范化的設計管理中，設計文件圖樣必須遵守相應的國家標準，如《電子產品圖樣繪制規則》、《設計文件管理制圖》和《印制板制圖》等，而由于Protel軟件都是英文版，因此無法直接打印出符合國家標準的圖紙，要將圖紙規范化常用的方式是套打，即先將符合國家標準的表和漢字等打在紙上，再將該紙放入打印機，用Protel軟件將印制板圖打印其上，形成符合標準的文件，但這種做法效率很低，而且圖形常會打偏，有時甚至會打反，經筆者試驗，找到了一種簡便的方法，使印制板圖轉換為AUTOCAD格式，再在AUTOCAD里一次性打印出符合標準的圖紙。
上傳時間： 2013-10-12
上傳用戶：Wwill
Abstract: With the large number of analog switches on the market today, there are many performance criteria for a product designer to consider. This application note reviews the basic construction of
上傳時間： 2013-11-09
上傳用戶：xiaohanhaowei
The MAX17600–MAX17605 devices are high-speedMOSFET drivers capable of sinking /sourcing 4A peakcurrents. The devices have various inverting and noninvertingpart options that provide greater flexibility incontrolling the MOSFET. The devices have internal logiccircuitry that prevents shoot-through during output-statchanges. The logic inputs are protected against voltagespikes up to +14V, regardless of VDD voltage. Propagationdelay time is minimized and matched between the dualchannels. The devices have very fast switching time,combined with short propagation delays (12ns typ),making them ideal for high-frequency circuits. Thedevices operate from a +4V to +14V single powersupply and typically consume 1mA of supply current.The MAX17600/MAX17601 have standard TTLinput logic levels, while the MAX17603 /MAX17604/MAX17605 have CMOS-like high-noise margin (HNM)input logic levels. The MAX17600/MAX17603 are dualinverting input drivers, the MAX17601/MAX17604 aredual noninverting input drivers, and the MAX17602 /MAX17605 devices have one noninverting and oneinverting input. These devices are provided with enablepins (ENA, ENB) for better control of driver operation.
上傳時間： 2013-12-20
上傳用戶：zhangxin
The LT®6552 is a specialized dual-differencing 75MHzoperational amplifier ideal for rejecting common modenoise as a video line receiver. The input pairs are designedto operate with equal but opposite large-signal differencesand provide exceptional high frequency commonmode rejection (CMRR of 65dB at 10MHz), therebyforming an extremely versatile gain block structure thatminimizes component count in most situations. The dualinput pairs are free to take on independent common modelevels, while the two voltage differentials are summedinternally to form a net input signal.
上傳時間： 2014-12-23
上傳用戶：13691535575
Photodiodes can be broken into two categories: largearea photodiodes with their attendant high capacitance(30pF to 3000pF) and smaller area photodiodes withrelatively low capacitance (10pF or less). For optimalsignal-to-noise performance, a transimpedance amplifi erconsisting of an inverting op amp and a feedback resistoris most commonly used to convert the photodiode currentinto voltage. In low noise amplifi er design, large areaphotodiode amplifi ers require more attention to reducingop amp input voltage noise, while small area photodiodeamplifi ers require more attention to reducing op amp inputcurrent noise and parasitic capacitances.
上傳時間： 2013-10-28
上傳用戶：hanbeidang
One of the most critical components in a step-up design like Figure 1 is the transformer. Transformers have parasitic components that can cause them to deviate from their ideal characteristics, and the parasitic capacitance associated with the secondary can cause large resonating current spikes on the leading edge of the switch current waveform.
上傳時間： 2013-11-22
上傳用戶：15070202241
通過安裝和調試ＥＣＧ放大器，了解醫學信號放大器的特點，并掌握放大器的有關指標。 安裝和調試后的ＥＣＧ放大器，應達到以下指標： １?具有較高輸入阻抗＞１ＭΩ ２?放大器差動增益約為１０００ ３?具有較高共模抑制比（CMRR>80db） ４?等效輸入噪聲＜１０μＶ ５?頻帶范圍０.０５Ｈｚ～１００Ｈｚ
上傳時間： 2013-10-18
上傳用戶：taiyang250072
使用時鐘PLL的源同步系統時序分析一）回顧源同步時序計算Setup Margin = Min Clock Etch Delay – Max Data Etch Delay – Max Delay Skew – Setup TimeHold Margin = Min Data Etch Delay – Max Clock Etch Delay + Min Delay Skew + Data Rate – Hold Time下面解釋以上公式中各參數的意義：Etch Delay：與常說的飛行時間(Flight Time)意義相同，其值并不是從仿真直接得到，而是通過仿真結果的后處理得來。請看下面圖示：圖一為實際電路，激勵源從輸出端，經過互連到達接收端，傳輸延時如圖示Rmin，Rmax，Fmin，Fmax。圖二為對應輸出端的測試負載電路，測試負載延時如圖示Rising，Falling。通過這兩組值就可以計算得到Etch Delay 的最大和最小值。
上傳時間： 2013-11-05
上傳用戶：VRMMO
