The purpose of this project is to explore the issues and implementation of a multiple instruction stream, single data stream processor. We are running two instruction streams on two CPUs which share an address space. The processors share a second level cache, and maintain coherence at the L1 cache with a write-invalidate policy. The L2 cache is two-way set associative, with a block size of 8 words, and a total capacity of 512 words.
ecos RTOS 原理介紹和應用開發The design philosophy of eCos was to augment an open-source RTOS (which meant no
per-unit royalties) with source-level con?guration tools that would enable embedded developers
to scale their RTOS from hundreds of bytes to hundreds of kilobytes without needing to manu-
ally change a line of source code.
The use of hardware description languages (HDLs) is becoming
increasingly common for designing and verifying FPGA designs.
Behavior level description not only increases design productivity, but also
provides unique advantages for design verification. The most dominant
HDLs today are Verilog and VHDL. This application note illustrates the
use of Verilog in the design and verification of a digital UART (Universal
Asynchronous Receiver & Transmitter).
This document specifies a subset of the C programming language which is intended to be suitable
for embedded automotive systems up to and including safety integrity level 3 (as defined in the
MISRA Guidelines). It contains a list of rules concerning the use of the C programming language
together with justifications and examples.
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The
W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the
contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary
ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4-
bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight
sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the
W78E58B allows the program memory to be programmed and read electronically. Once the code is
confirmed, the user can protect the code for security
Heapsort
1.A heap is a binary tree satisfying the followingconditions:
-This tree is completely balanced.
-If the height of this binary tree is h, then leaves can be at level h or level h-1.
-All leaves at level h are as far to the left as possible.
-The data associated with all descendants of a node are smaller than the datum associated with this node.
Implementation
1.using a linear array not a binary tree.
-The sons of A(h) are A(2h) and A(2h+1).
2.time complexity: O(n log n)
