本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時(shí)間： 2013-10-31
上傳用戶：yy_cn
注:1.這篇文章斷斷續(xù)續(xù)寫了很久,畫圖技術(shù)也不精,難免錯(cuò)漏,大家湊合看.有問(wèn)題可以留言. 2.論壇排版把我的代碼縮進(jìn)全弄沒(méi)了,大家將代碼粘貼到arduino編譯器,然后按ctrl+T重新格式化代碼格式即可看的舒服. 一、什么是PWM PWM 即Pulse Wavelength Modulation 脈寬調(diào)制波，通過(guò)調(diào)整輸出信號(hào)占空比，從而達(dá)到改 變輸出平均電壓的目的。相信Arduino 的PWM 大家都不陌生，在Arduino Duemilanove 2009 中，有6 個(gè)8 位精度PWM 引腳，分別是3, 5, 6, 9, 10, 11 腳。我們可以使用analogWrite()控 制PWM 腳輸出頻率大概在500Hz 的左右的PWM 調(diào)制波。分辨率8 位即2 的8 次方等于 256 級(jí)精度。但是有時(shí)候我們會(huì)覺(jué)得6 個(gè)PWM 引腳不夠用。比如我們做一個(gè)10 路燈調(diào)光， 就需要有10 個(gè)PWM 腳。Arduino Duemilanove 2009 有13 個(gè)數(shù)字輸出腳，如果它們都可以 PWM 的話，就能滿足條件了。于是本文介紹用軟件模擬PWM。 二、Arduino 軟件模擬PWM Arduino PWM 調(diào)壓原理：PWM 有好幾種方法。而Arduino 因?yàn)殡娫春蛯?shí)現(xiàn)難度限制，一般 使用周期恒定，占空比變化的單極性PWM。 通過(guò)調(diào)整一個(gè)周期里面輸出腳高/低電平的時(shí)間比（即是占空比）去獲得給一個(gè)用電器不同 的平均功率。 如圖所示，假設(shè)PWM 波形周期1ms（即1kHz），分辨率1000 級(jí)。那么需要一個(gè)信號(hào)時(shí)間 精度1ms/1000=1us 的信號(hào)源，即1MHz。所以說(shuō)，PWM 的實(shí)現(xiàn)難點(diǎn)在于需要使用很高頻的 信號(hào)源，才能獲得快速與高精度。下面先由一個(gè)簡(jiǎn)單的PWM 程序開(kāi)始： const int PWMPin = 13; int bright = 0; void setup() { pinMode(PWMPin, OUTPUT); } void loop() { if((bright++) == 255) bright = 0; for(int i = 0; i < 255; i++) { if(i < bright) { digitalWrite(PWMPin, HIGH); delayMicroseconds(30); } else { digitalWrite(PWMPin, LOW); delayMicroseconds(30); } } } 這是一個(gè)軟件PWM 控制Arduino D13 引腳的例子。只需要一塊Arduino 即可測(cè)試此代碼。 程序解析：由for 循環(huán)可以看出，完成一個(gè)PWM 周期，共循環(huán)255 次。 假設(shè)bright=100 時(shí)候，在第0~100 次循環(huán)中，i 等于1 到99 均小于bright，于是輸出PWMPin 高電平； 然后第100 到255 次循環(huán)里面，i 等于100~255 大于bright，于是輸出PWMPin 低電平。無(wú) 論輸出高低電平都保持30us。 那么說(shuō)，如果bright=100 的話，就有100 次循環(huán)是高電平，155 次循環(huán)是低電平。 如果忽略指令執(zhí)行時(shí)間的話，這次的PWM 波形占空比為100/255，如果調(diào)整bright 的值， 就能改變接在D13 的LED 的亮度。 這里設(shè)置了每次for 循環(huán)之后，將bright 加一，并且當(dāng)bright 加到255 時(shí)歸0。所以，我們 看到的最終效果就是LED 慢慢變亮，到頂之后然后突然暗回去重新變亮。 這是最基本的PWM 方法，也應(yīng)該是大家想的比較多的想法。 然后介紹一個(gè)簡(jiǎn)單一點(diǎn)的。思維風(fēng)格完全不同。不過(guò)對(duì)于驅(qū)動(dòng)一個(gè)LED 來(lái)說(shuō)，效果與上面 的程序一樣。 const int PWMPin = 13; int bright = 0; void setup() { pinMode(PWMPin, OUTPUT); } void loop() { digitalWrite(PWMPin, HIGH); delayMicroseconds(bright*30); digitalWrite(PWMPin, LOW); delayMicroseconds((255 - bright)*30); if((bright++) == 255) bright = 0; } 可以看出，這段代碼少了一個(gè)For 循環(huán)。它先輸出一個(gè)高電平，然后維持(bright*30)us。然 后輸出一個(gè)低電平，維持時(shí)間((255-bright)*30)us。這樣兩次高低就能完成一個(gè)PWM 周期。 分辨率也是255。 三、多引腳PWM Arduino 本身已有PWM 引腳并且運(yùn)行起來(lái)不占CPU 時(shí)間，所以軟件模擬一個(gè)引腳的PWM 完全沒(méi)有實(shí)用意義。我們軟件模擬的價(jià)值在于：他能將任意的數(shù)字IO 口變成PWM 引腳。 當(dāng)一片Arduino 要同時(shí)控制多個(gè)PWM，并且沒(méi)有其他重任務(wù)的時(shí)候，就要用軟件PWM 了。 多引腳PWM 有一種下面的方式： int brights[14] = {0}; //定義14個(gè)引腳的初始亮度，可以隨意設(shè)置 int StartPWMPin = 0, EndPWMPin = 13; //設(shè)置D0~D13為PWM 引腳 int PWMResolution = 255; //設(shè)置PWM 占空比分辨率 void setup() { //定義所有IO 端輸出 for(int i = StartPWMPin; i <= EndPWMPin; i++) { pinMode(i, OUTPUT); //隨便定義個(gè)初始亮度,便于觀察 brights[ i ] = random(0, 255); } } void loop() { //這for 循環(huán)是為14盞燈做漸亮的。每次Arduino loop()循環(huán)， //brights 自增一次。直到brights=255時(shí)候，將brights 置零重新計(jì)數(shù)。 for(int i = StartPWMPin; i <= EndPWMPin; i++) { if((brights[i]++) == PWMResolution) brights[i] = 0; } for(int i = 0; i <= PWMResolution; i++) //i 是計(jì)數(shù)一個(gè)PWM 周期 { for(int j = StartPWMPin; j <= EndPWMPin; j++) //每個(gè)PWM 周期均遍歷所有引腳 { if(i < brights[j])\ 所以我們要更改PWM 周期的話，我們將精度（代碼里面的變量：PWMResolution）降低就行，比如一般調(diào)整LED 亮度的話，我們用64 級(jí)精度就行。這樣速度就是2x32x64=4ms。就不會(huì)閃了。
上傳時(shí)間： 2013-10-08
上傳用戶：dingdingcandy
超聲波傳感器適用于對(duì)大幅的平面進(jìn)行靜止測(cè)距。普通的超聲波傳感器測(cè)距范圍大概是 2cm~450cm，分辨率3mm（淘寶賣家說(shuō)的，筆者測(cè)試環(huán)境沒(méi)那么好，個(gè)人實(shí)測(cè)比較穩(wěn)定的 距離10cm~2m 左右，超過(guò)此距離就經(jīng)常有偶然不準(zhǔn)確的情況發(fā)生了，當(dāng)然不排除筆者技術(shù) 問(wèn)題。） 測(cè)試對(duì)象是淘寶上面最便宜的SRF-04 超聲波傳感器，有四個(gè)腳：5v 電源腳（Vcc），觸發(fā)控制端（Trig），接收端（Echo），地端（GND） 附:SRF 系列超聲波傳感器參數(shù)比較 模塊工作原理： 采用IO 觸發(fā)測(cè)距，給至少10us 的高電平信號(hào)； 模塊自動(dòng)發(fā)送8個(gè)40KHz 的方波，自動(dòng)檢測(cè)是否有信號(hào)返回； 有信號(hào)返回，通過(guò)IO 輸出一高電平，高電平持續(xù)的時(shí)間就是超聲波從發(fā)射到返回的時(shí)間．測(cè)試距離=(高電平時(shí)間*聲速(340m/s))/2; 電路連接方法 Arduino 程序例子： constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { Serial.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低電平發(fā)一個(gè)短時(shí)間脈沖去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //將回波時(shí)間換算成cm cm = (int(cm * 100.0)) / 100.0; //保留兩位小數(shù) Serial.print(cm); Serial.print("cm"); Serial.println(); delay(1000); }
上傳時(shí)間： 2013-10-18
上傳用戶：星仔
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上傳時(shí)間： 2013-11-08
上傳用戶：immanuel2006
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-14
上傳用戶：zoudejile
Abstract: Designers who must interface 1-Wire temperature sensors with Xilinx field-programmable gate arrays(FPGAs) can use this reference design to drive a DS28EA00 1-Wire slave device. The downloadable softwarementioned in this document can also be used as a starting point to connect other 1-Wire slave devices. The systemimplements a 1-Wire master connected to a UART and outputs temperature to a PC from the DS28EA00 temperaturesensor. In addition, high/low alarm outputs are displayed from the DS28EA00 PIO pins using LEDs.
標(biāo)簽： PicoBlaze Create Master Xilinx
上傳時(shí)間： 2013-11-12
上傳用戶：大三三
Designing withProgrammable Logicin an Analog WorldProgrammable logic devices revolutionizeddigital design over 25 years ago,promising designers a blank chip todesign literally any function and programit in the field. PLDs can be low-logicdensity devices that use nonvolatilesea-of-gates cells called complexprogrammable logic devices (CPLDs)or they can be high-density devicesbased on SRAM look-up tables (LUTs)
標(biāo)簽： Solutions Analog Altera FPGAs
上傳時(shí)間： 2013-10-27
上傳用戶：fredguo
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標(biāo)簽： Solutions Analog Xilinx FPGAs
上傳時(shí)間： 2013-11-07
上傳用戶：suicone
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上傳時(shí)間： 2013-11-11
上傳用戶：csgcd001
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