Link & System-Level Wireless OFDM System Simulator Version，仿真了OFDM
標簽： System-Level Simulator Wireless Version
上傳時間： 2013-12-18
上傳用戶：xg262122
Ideal for large low power (nanoWatt) and connectivity applications that benefit from the availability of four serial ports: double synchronous serial ports (I² C™ and SPI™ ) and double asynchronous (LIN capable) serial ports. Large amounts of RAM memory for buffering and FLASH program memory make it ideal for instrumentation panels, TCP/IP enabled embedded applications as well as metering and industrial control and monitoring applications. While operating up to 40 MHz, it is also backward software and hardware compatible with the PIC18F8720.
標簽： connectivity applications availabilit nanoWatt
上傳時間： 2016-02-04
上傳用戶：CHINA526
Designing a Low-Cost USB Mouse with the Cypress Semiconductor CY7C63000 USB Controller
標簽： Semiconductor Controller Designing USB
上傳時間： 2016-02-10
上傳用戶：亞亞娟娟123
Level Crossing Rate in Terms of the Characteristic Function: A New Approach for Calculating the Fading Rate in Diversity Systems
標簽： Characteristic Calculating the Crossing
上傳時間： 2016-02-19
上傳用戶：shinesyh
Implicit and Non-parametric Shape Reconstruction from Unorganized Data using a Variational Level Set Method
標簽： Non-parametric Reconstruction Unorganized Variational
上傳時間： 2016-03-02
上傳用戶：wangdean1101
SDRAM 參考設計:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
標簽： high-level following reference diagram
上傳時間： 2013-12-15
上傳用戶：Miyuki
Digital Signal Processing System Level Design Using LabVIEW，基于LabViEW的數(shù)字信號處理系統(tǒng)設計參考書。
標簽： Processing Digital LabVIEW Design
上傳時間： 2016-03-03
上傳用戶：edisonfather
使用遞迴運算畫出fractal tree,使用者可自行輸入遞迴次數(shù),畫出不同level的tr
上傳時間： 2014-12-01
上傳用戶：wang0123456789
基于OFDM的無線寬帶系統(tǒng)仿真It contains mainly two parts, i.e. link-level simulator and system-level simulator. Link-level simulator focus on a single-cell single-user scenario, where signal is transmitted from tx, and estimated at rx. Comparing the difference in tx/rx signal, the error rate can be found out. The output of the link-level simulator is the BLER/BER vs. SNR mapping table, that can be used for the system-level simulation. System-level simulator focus on a multi-cell multi-user scenario. For the sake of simplicity, it takes the mapping table aquired in the link-level simulation, measure the actural SNR, and finds the corresponding error rate.
標簽： simulator i.e. system-level link-level
上傳時間： 2016-03-15
上傳用戶：xsnjzljj
SD卡讀寫的VHDL VHDL Source Files in Smartcard: Top.vhd - top level file smartcard.vhd conver2ascii.vhd binary2bcd.vhd lcd.vhd power_up.vhd
標簽： VHDL conver2asci Smartcard vhd
上傳時間： 2016-03-15
上傳用戶：fxf126@126.com
