Capturing low-level network data can be hard in Java, but it s certainly not impossible If you want to capture network packets in your Java program, you ll need a little help because no parts of the core Java APIAPI give access to low-level network
標(biāo)簽： impossible Capturing low-level certainly
上傳時間： 2016-03-05
上傳用戶：yuanyuan123
the FXT library: fast transforms and low level algorithms. The package contains many algorithms for programmers: bit manipulation, fast othogonal transforms, arithmetic and number theory algorithms.
標(biāo)簽： algorithms transforms contains library
上傳時間： 2014-01-09
上傳用戶：星仔
A New Optimization Model for Dynamic Power and Sub-Carrier
標(biāo)簽： Optimization Sub-Carrier Dynamic Model
上傳時間： 2014-01-01
上傳用戶：jiahao131
1、項目背景：數(shù)據(jù)庫原理課程設(shè)計 2、編寫目的：掌握數(shù)據(jù)庫設(shè)計原理及相關(guān)軟件的使用 3、軟件定義：學(xué)生信息管理系統(tǒng) 4、開發(fā)環(huán)境：Power builder 9.0
標(biāo)簽： builder Power 9.0 項目
上傳時間： 2016-03-17
上傳用戶：123啊
XILINX 2K Series 在POWER PCB 開發(fā)環(huán)境下使用 非常好的 XILINX CPLD 源代碼
標(biāo)簽： XILINX Series POWER CPLD
上傳時間： 2016-03-22
上傳用戶：問題問題
wince power manager source code
標(biāo)簽： manager source wince power
上傳時間： 2016-04-01
上傳用戶：lyy1234
lpc源代碼verilog實現(xiàn)的。操作low pin count設(shè)備
標(biāo)簽： verilog count lpc low
上傳時間： 2013-12-20
上傳用戶：稀世之寶039
Fast settling-time added to the already conflicting requirements of narrow channel spacing and low phase noise lead to Fractional4 divider techniques for PLL synthesizers. We analyze discrete "beat-note spurious levels from arbitrary modulus divide sequences including those from classic accumulator methods.
標(biāo)簽： settling-time requirements conflicting already
上傳時間： 2016-04-14
上傳用戶：liansi
Discrete Fourier Transform and Power Spectrum Calculates Power Spectrum from a Time Series
標(biāo)簽： Spectrum Power Calculates Transform
上傳時間： 2014-01-21
上傳用戶：woshini123456
power pc 405 ep核心板及其周邊的原理圖和pcb圖
上傳時間： 2013-12-13
上傳用戶：lingzhichao
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