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1.The C Programming Language is a powerful, flexible andpotentially portable high-level programming language. 2.The C language may be used successfully to create a programfor an 8-bit MCU, but to produce the most efficient machinecode, the programmer must carefully construct the C Languageprogram.3.The programmer must not only create an efficient high leveldesign, but also pay attention to the detailed implementation.
標(biāo)簽：
FREESCALE
單片機(jī)
編程
教程
上傳時(shí)間：
2013-12-27
上傳用戶：huanglang
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匯編器在微處理器的驗(yàn)證和應(yīng)用中舉足輕重，如何設(shè)計(jì)通用的匯編器一直是研究的熱點(diǎn)之一。本文提出了一種開放式的匯編器系統(tǒng)設(shè)計(jì)思想，在匯編語(yǔ)言與機(jī)器語(yǔ)言間插入中間代碼CMDL（code mapping description language）語(yǔ)言，打破匯編語(yǔ)言與機(jī)器語(yǔ)言的直接映射關(guān)系，由此建立起一套描述匯編語(yǔ)言與機(jī)器語(yǔ)言的開放式映射體系。基于此開放式映射體系開發(fā)了一套匯編器系統(tǒng)，具有較高層次上的通用性和可移植性。【關(guān)鍵詞】指令集，CMDL，匯編器，開放式
Design of Retargetable Assembler System Liu Ling Feng Wen Nan Wang Ying Chun Jiang An Ping Ji Li Jiu IME of Peking University, 100871【摘要】An assembler plays a very important role in the field of microprocessor verifications and applications, thus how to build a retargetable assembler system has been a hotspot in this field for long time. This paper presents a new method about the retargetable assembler system design.It provides a kind of language CMDL, code mapping description language. During the process of assembling, assembler languages are firstly translated to CMDL, and then mapped to the machine codes. In an other word, CMDL is inserted between assembler languages and machine codes during the translation procedure. As a medium code, CMDL has a lot of features, such as high extraction, strong descript capabilities. It can describe almost all attributes of assembler languages. By breaking the direct mapping relationship between assembler languages and machine codes, the complexities of machine codes are hided to the users, therefore, the new retargetable assembler system has higher retargetable level by converting the mapping from assembler languages and machine codes to assembler languages and CMDL, and implementationof it becomes easier. Based on the new mapping system structure, a retargetable assemblersystem is developed. It proved the whole system has good retargetability and implantability.【關(guān)鍵詞】instruction set, symbol table, assembler, lexical analysis, retargetability
標(biāo)簽：
開放式
匯編器
上傳時(shí)間：
2013-10-10
上傳用戶：meiguiweishi
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The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標(biāo)簽：
4channel
multiple
9544A
9544
上傳時(shí)間：
2014-12-28
上傳用戶：潛水的三貢
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The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽：
switch
Octal
9549
with
上傳時(shí)間：
2014-11-22
上傳用戶：xcy122677
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The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
標(biāo)簽：
channel
9548A
9548
PCA
上傳時(shí)間：
2013-10-13
上傳用戶：bakdesec
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The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for
SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register,
8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption
and a high-impedance open-drain output pin, IO0.
The system master can enable the PCA9557’s I/O as either input or output by writing to
the configuration register. The system master can also invert the PCA9557 inputs by
writing to the active HIGH polarity inversion register. Finally, the system master can reset
the PCA9557 in the event of a time-out by asserting a LOW in the reset input.
The power-on reset puts the registers in their default state and initializes the
I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to
occur without de-powering the part.
標(biāo)簽：
C-bus
SMBus
reset
port
上傳時(shí)間：
2014-01-18
上傳用戶：bs2005
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本文簡(jiǎn)單介紹了MCGS 組態(tài)軟件和SPCE061A 單片機(jī)的特點(diǎn)，即北京昆侖通態(tài)自動(dòng)化軟件科技有限公司的工控組態(tài)軟件MCGS(Monitor and Control Generated System )和臺(tái)灣凌陽(yáng)科技推出的16 位微控制器SPCE061A，重點(diǎn)介紹了如何一步步開發(fā)SPCE061A 單片機(jī)的驅(qū)動(dòng)程序，并簡(jiǎn)單介紹了下位機(jī)程序的設(shè)計(jì)，最后給出了測(cè)試情況。計(jì)算機(jī)技術(shù)的飛速發(fā)展為工業(yè)自動(dòng)化開辟了廣闊的發(fā)展空間，人們可以快捷地開發(fā)和組建高效的控制系統(tǒng)。筆者設(shè)計(jì)的液體點(diǎn)滴監(jiān)控模型,可以對(duì)液體點(diǎn)滴情況實(shí)現(xiàn)遠(yuǎn)程監(jiān)控和現(xiàn)場(chǎng)監(jiān)控，終端和上位機(jī)均可人工設(shè)定所需的液體點(diǎn)滴速度并動(dòng)態(tài)顯示。在這方面，MCGS 工控組態(tài)軟件提供了強(qiáng)有力的支持，它是一套Windows 環(huán)境下快速構(gòu)造和生成上位機(jī)監(jiān)控系統(tǒng)的組態(tài)軟件系統(tǒng)，可快速構(gòu)造和生成數(shù)據(jù)采集、報(bào)警處理、流程控制、動(dòng)畫顯示、報(bào)表輸出等界面,實(shí)現(xiàn)各種工程曲線的繪制、報(bào)表輸出、遠(yuǎn)程通信等功能 [1]。MCGS 作為一種方便有效的通用工控軟件,它提供了國(guó)內(nèi)外各種常用的工控設(shè)備的驅(qū)動(dòng)程序。但在實(shí)際應(yīng)用中,因?yàn)樗迷O(shè)備的特殊性,允許用戶根據(jù)需要來定制設(shè)備驅(qū)動(dòng)程序。MCGS 用Active DLL 構(gòu)件實(shí)現(xiàn)設(shè)備驅(qū)動(dòng)程序,通過規(guī)范的OLE 接口掛接到MCGS 中,使其構(gòu)成一個(gè)整體。鑒于Visual Basic 語(yǔ)言的通用性和簡(jiǎn)單性,使用VB 來開發(fā)單片機(jī)驅(qū)動(dòng),MCGS 的實(shí)現(xiàn)方法和原理與標(biāo)準(zhǔn)的Active DLL 完全一致,但MCGS 規(guī)定了一套接口規(guī)范,只有遵守這些接口規(guī)范的Active DLL 才能用作MCGS 的設(shè)備驅(qū)動(dòng)構(gòu)件。利用具有語(yǔ)音和 DSP 功能的SPCE061A 單片機(jī)作為液體點(diǎn)滴監(jiān)控模型的核心控制器，SPCE061A 是臺(tái)灣凌陽(yáng)科技推出的16 位微控制器，提供了豐富的軟、硬件資源，開發(fā)靈活方便。除此之外SPCE061A 的最高時(shí)鐘頻率可達(dá)到49MHz,具有運(yùn)算速度高的優(yōu)勢(shì)，這為語(yǔ)音的錄制和播放提供了條件[4]。
標(biāo)簽：
MCGS
凌陽(yáng)單片機(jī)
驅(qū)動(dòng)程序
上傳時(shí)間：
2013-12-19
上傳用戶：leesuper
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All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽：
Signal
Input
Fall
Rise
上傳時(shí)間：
2013-10-23
上傳用戶：copu
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All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽：
C16x
微控制器
輸入信號(hào)
時(shí)序圖
上傳時(shí)間：
2014-04-02
上傳用戶：han_zh
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The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
標(biāo)簽：
3.3
看門狗
芯片
上傳時(shí)間：
2013-10-22
上傳用戶：taiyang250072
