This paper presents several low-latency mixed-Timing
FIFO (first-in–first-out) interfaces designs that interface systems
on a chip working at different speeds. The connected systems
can be either synchronous or asynchronous. The designs are then
adapted to work between systems with very long interconnect
delays, by migrating a single-clock solution by Carloni et al.
(1999, 2000, and 2001) (for “latency-insensitive” protocols) to
mixed-Timing domains. The new designs can be made arbitrarily
robust with regard to metastability and interface operating speeds.
Initial simulations for both latency and throughput are promising.
This a GA implementation using binary and real coded variables. Mixed variables can be used. Constraints can also be handled. All constraints must be greater-than-equal-to type (g >= 0) and normalized (see the sample problem in prob1 in objective()).
The I2C Memory Model is a generic Proteus VSM model designed to model the timing and functionality of I2C memory devices from a wide range of manufacturers.
* KeyDebounce Accept new key reading, handle timing for debounce & slew
* KeyId Report which key is currently pressed
* KeySlewTimeSet Accept slew time for key currently pressed
