中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標(biāo)簽： Spartan-XL Express XAPP FPGA
上傳時(shí)間： 2015-01-02
上傳用戶：nanxia
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時(shí)間： 2013-11-23
上傳用戶：shen_dafa
歡迎使用 PowerPCB 教程。本教程描述了 PADS-PowerPCB 的絕大部分功能和特點(diǎn)，以及使用的各個(gè)過程，這些功能包括： · 基本操作 · 建立元件(Component) · 建立板子邊框線(Board outline) · 輸入網(wǎng)表(Netlist) · 設(shè)置設(shè)計(jì)規(guī)則(Design Rule) · 元件(Part)的布局(Placement) · 手工和交互的布線 · SPECCTRA全自動布線器(Route Engine) · 覆銅(Copper Pour) · 建立分隔/混合平面層(Split/mixed Plane) · Microsoft的目標(biāo)連接與嵌入(OLE)(Object Linking Embedding) · 可選擇的裝配選件(Assembly options) · 設(shè)計(jì)規(guī)則檢查(Design Rule Check) · 反向標(biāo)注(Back Annotation) · 繪圖輸出(Plot Output) 使用本教程后，你可以學(xué)到印制電路板設(shè)計(jì)和制造的許多基本知識。
上傳時(shí)間： 2013-10-08
上傳用戶：x18010875091
隨著系統(tǒng)設(shè)計(jì)復(fù)雜性和集成度的大規(guī)模提高，電子系統(tǒng)設(shè)計(jì)師們正在從事100MHZ以上的電路設(shè)計(jì)，總線的工作頻率也已經(jīng)達(dá)到或者超過50MHZ，有一大部分甚至超過100MHZ。目前約80% 的設(shè)計(jì)的時(shí)鐘頻率超過50MHz，將近50% 以上的設(shè)計(jì)主頻超過120MHz，有20%甚至超過500M。當(dāng)系統(tǒng)工作在50MHz時(shí)，將產(chǎn)生傳輸線效應(yīng)和信號的完整性問題；而當(dāng)系統(tǒng)時(shí)鐘達(dá)到120MHz時(shí)，除非使用高速電路設(shè)計(jì)知識，否則基于傳統(tǒng)方法設(shè)計(jì)的PCB將無法工作。因此，高速電路信號質(zhì)量仿真已經(jīng)成為電子系統(tǒng)設(shè)計(jì)師必須采取的設(shè)計(jì)手段。只有通過高速電路仿真和先進(jìn)的物理設(shè)計(jì)軟件，才能實(shí)現(xiàn)設(shè)計(jì)過程的可控性。傳輸線效應(yīng)基于上述定義的傳輸線模型，歸納起來，傳輸線會對整個(gè)電路設(shè)計(jì)帶來以下效應(yīng)。 · 反射信號Reflected signals · 延時(shí)和時(shí)序錯(cuò)誤Delay & Timing errors · 過沖(上沖/下沖)Overshoot/Undershoot · 串?dāng)_Induced Noise (or crosstalk) · 電磁輻射EMI radiation
標(biāo)簽： 高速電路 傳輸線 效應(yīng)分析
上傳時(shí)間： 2013-11-05
上傳用戶：tzrdcaabb
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
上傳時(shí)間： 2013-11-01
上傳用戶：ouyang426
One of the most important issues affecting the implementation of microcontroller software deals with the data-decision algorithm. Data-decision refers to decoding the DIO-pin from the CC400/CC900. Two main principles exist for decoding Manchester-coded data: Data decision based on timing the period between transitions, and data decision based on oversampling.
標(biāo)簽： microcontroller implementation important affecting
上傳時(shí)間： 2013-12-18
上傳用戶：671145514
This project is created using the Keil ARM CA Compiler. The Logic Analyzer built into the simulator may be used to monitor and display any variable or peripheral I/O register. It is already configured to show the PWM output signal on PORT3.0 and PORT3.1 This ARM Example may be debugged using only the uVision Simulator and your PC--no additional hardware or evaluation boards are required. The Simulator provides cycle-accurate simulation of all on-chip peripherals of the ADuC7000 device series. You may create various input signals like digital pulses, sine waves, sawtooth waves, and square waves using signal functions which you write in C. Signal functions run in the background in the simulator within timing constraints you configure. In this example, several signal functions are defined in the included Startup_SIM.INI file.
標(biāo)簽： the Analyzer Compiler project
上傳時(shí)間： 2013-12-19
上傳用戶：Yukiseop
Attributes, Constraints, and Carry Logic Overview Information for Mentor Customers Schematic Syntax UCF/NCF File Syntax Attributes/Logical Constraints Placement Constraints Relative Location (RLOC) Constraints Timing Constraints Physical Constraints Relationally Placed Macros (RPM) Carry Logic in XC4000 FPGAs Carry Logic in XC5200 FPGAs
標(biāo)簽： Constraints Information Attributes Customers
上傳時(shí)間： 2015-05-12
上傳用戶：cc1015285075
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