電學中的測量技術涉及范圍非常廣,電流測量在電學計量中占有非常重要的位置。如何精確地進行電流測量是精密測量的一大難題。傳統的電流檢測電路多采用運算放大芯片與片外電流檢測電路相結合的方式,電路集成度很低,需要較多的接口和資源才能完成對電路的檢測。本文把所有電路部分都集成在一塊芯片上,包括檢測電阻,運算放大器電路及模擬轉數字轉換電路,從而在電路內部可以進行電流檢測,使電路更好的集成化。前置電路使用二級共源共柵結構的運算放大器,減小溝道長度調制效應造成的電流誤差。10位SAR ADC中采用電容驅動能力強的傳輸門保證了模數轉化器的有效精度。比較器模塊采用再生鎖存器與遲滯比較器作為基礎單元組合解決精密測量的問題。本設計可以作為嵌入芯片內的一小部分而檢測芯片中的微小電流1mA~100mA,工作電壓在1.8v左右,電流檢測精度預期達到10uA的需求。The measurement technology in electricity involves a wide range,and current measurement plays a very important position in electrical measurement.How to accurately measure current is a big problem in precision measurement. The traditional current detecting circuit adopts the combination of the operational amplifier chip and theoff-chip current detecting circuit, The circuit integration is very low, and more interfaces and resources are needed tocomplete the circuit detection.This topic integrates all the circuit parts into one chip, including detection resistance, operational amplifier circuit andanalog to digital conversion circuit. Highly integrated circuit makes the external resources on the chip more intensive,so that current detection can be carried out inside the circuit, so that the circuit can be better integrated. Thefront-end circuit of this project uses two-stage cascade operational amplifier and cascade tube to reduce the currenterror caused by channel length modulation effect. In 10-bit SAR ADC, the transmission gate with strong capacitivedriving ability ensures the effective accuracy of the analog-to-digital converter. Comparator module uses regenerativelatch and hysteresis comparator as basic unit to solve the difficult problem of precision measurement. This topic can beused as a small part of the embedded chip to detect the micro-current in the chip 1 mA~100 mA, the working voltageis about 1.8v, and the current detection accuracy is expected to reach the requirement of 10 uA.
標簽：
電流檢測
電路
運算放大器
adc
上傳時間：
2022-04-03
上傳用戶：
le flows through MOS channel while Ih flows across PNP transistor Ih= a/(1-a) le, IE-le+lh=1/(1-a)' le Since IGBT has a long base PNP, a is mainly determined by ar si0 2ar= 1/cosh(1/La), La: ambipolar diff length a-0.5 (typical value)p MOSFET channel current (saturation), le=U"Cox"W(2"Lch)"(Vc-Vth)le Thus, saturated collector current Ic, sat=1/(1-a)"le=-1/(1-a)"UCox"W/(2Lch)"(Vo-Vth)2Also, transconductance gm, gm= 1/(1-a)"u' Cox W/Lch*(Vo-Vth)Turn-On1. Inversion layer is formed when Vge>Vth2. Apply positive collector bias, +Vce3. Electrons flow from N+ emitter to N-drift layer providing the base current for the PNP transistor4. Since J1 is forward blased, hole carriers are injected from the collector (acts as an emitter).5. Injected hole carriers exceed the doping level of N-drift region (conductivity modulation). Turn-Off1. Remove gate bias (discharge gate)2. Cut off electron current (base current, le, of pnp transistor)
標簽：
igbt
上傳時間：
2022-06-20
上傳用戶：wangshoupeng199
