most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPLD softwareimplementation (CPLDFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPLD utilization.
上傳時間： 2014-01-11
上傳用戶：a471778
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時間： 2013-10-22
上傳用戶：aeiouetla
One of the most misunderstood constructs in the Verilog language is the nonblockingassignment. Even very experienced Verilog designers do not fully understand how nonblockingassignments are scheduled in an IEEE compliant Verilog simulator and do not understand whenand why nonblocking assignments should be used. This paper details how Verilog blocking andnonblocking assignments are scheduled, gives important coding guidelines to infer correctsynthesizable logic and details coding styles to avoid Verilog simulation race conditions
上傳時間： 2013-11-01
上傳用戶：xzt
This document was developed under the Standard Hardware and Reliability Program (SHARP) TechnologyIndependent Representation of Electronic Products (TIREP) project. It is intended for use by VHSIC HardwareDescription Language (VHDL) design engineers and is offered as guidance for the development of VHDL modelswhich are compliant with the VHDL Data Item Description (DID DI-EGDS-80811) and which can be providedto manufacturing engineering personnel for the development of production data and the subsequent productionof hardware. most VHDL modeling performed to date has been concentrated at either the component level orat the conceptual system level. The assembly and sub-assembly levels have been largely disregarded. Under theSHARP TIREP project, an attempt has been made to help close this gap. The TIREP models are based upon lowcomplexity Standard Electronic Modules (SEM) of the format A configuration. Although these modules are quitesimple, it is felt that the lessons learned offer guidance which can readily be applied to a wide range of assemblytypes and complexities.
上傳時間： 2013-11-20
上傳用戶：pzw421125
波長信號的解調是實現光纖光柵傳感網絡的關鍵，基于現有的光纖光柵傳感器解調方法，提出一種基于FPGA的雙匹配光纖光柵解調方法，此系統是一種高速率、高精度、低成本的解調系統，并且通過引入雙匹配光柵有效地克服了雙值問題同時擴大了檢測范圍。分析了光纖光柵的測溫原理并給出了該方案軟硬件設計，綜合考慮系統的解調精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
上傳時間： 2013-10-10
上傳用戶：zxc23456789
Modern electronic systems solve so many difficult problems that they often seem like magic. Nonetheless, these systems all have thesame basic limitation: they need a source of electrical power! most of the time this is a straightforward challenge for the electronicdesigner, because there are many power-delivery solutions. Yet sometimes a device has no direct power source, and running wiresor replacing batteries is impractical. Even when long-life batteries are usable, they eventually need to be replaced, which requires aservice call.
標簽： 能量收集
上傳時間： 2015-01-03
上傳用戶：zukfu
There are many manufacturers of dot matrix LCD modules. However, most of these displaysare similar. They all have on-board controllers and drivers capable of displaying alpha numericsand a wide variety of other symbols (including Japanese "Katakana" characters). The internaloperation of LCD controller devices is determined by signals sent from a central processing unit(in this case, a CoolRunner-II CPLD).
標簽： CoolRunner-II XAPP 904 LCD
上傳時間： 2013-12-17
上傳用戶：haiya2000
This book introduces embedded systems to C and C++ programmers. Topics include testing memory devices, writing and erasing Flash memory, verifying nonvolatile memory contents, controlling on-chip peripherals, device driver design and implementation, optimizing embedded code for size and speed, and making the most of C++ without a performance penalty. Pages : 336 Slots : 1
標簽： programmers introduces embedded include
上傳時間： 2013-12-10
上傳用戶：shizhanincc
sheerdns is a master DNS server whose zone records are stored on a One-Record-Per-File bases. Because of this, it is the simplest of any DNS to configure, the easiest to update, and the most efficient for networks that experience a lot of updates (for example master servers for dynamic IP address ranges). You never have to restart it; any updates are available immediately without having to notify the sheerdns process. 來源: http://freshmeat.net/projects/sheerdns/?topic_id=149 sheerdns是一個主DNS服務器，它的域記錄保存在一個One-Record-Per-File（每文件一個記錄）的庫中。因此，它是最簡單的DNS配制，最容易更新，對于有大量更新的網絡（如動態IP地址范圍的主服務器）來說它是最高效的。你不必重新啟動它，任何更新不用通知對應DNS進程就可以立即生效。
標簽： One-Record-Per-File sheerdns records Becaus
上傳時間： 2015-01-10
上傳用戶：wyc199288
Tug of War(A tug of war is to be arranged at the local office picnic. For the tug of war, the picnickers must be divided into two teams. Each person must be on one team or the other the number of people on the two teams must not differ by more than 1 the total weight of the people on each team should be as nearly equal as possible. The first line of input contains n the number of people at the picnic. n lines follow. The first line gives the weight of person 1 the second the weight of person 2 and so on. Each weight is an integer between 1 and 450. There are at most 100 people at the picnic. Your output will be a single line containing 2 numbers: the total weight of the people on one team, and the total weight of the people on the other team. If these numbers differ, give the lesser first. )
上傳時間： 2014-01-07
上傳用戶：離殤
