CodeWarrior Development Tool Suites are comprehensive integrated developmentenvironments (IDE) that provide a highly visual and automated framework toaccelerate the development of the most complex embedded applications. Acrossmost stages of the development cycle, we offer tools to help configure, debug andoptimize your design built on Freescale MPUs, MCUs, DSPs and DSCs. These toolsuites provide solutions to get your design up and running fast.
標(biāo)簽： CodeWarrior 開發(fā)工具套件
上傳時間： 2013-11-07
上傳用戶：youlongjian0
The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8! Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects! This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever. Not just what to d why to do it! Use labview to build your own virtual workbench Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more Learn the "art" and best practices of effective labview development NEW: Streamline development with labview Express VIs NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽： Everyone LabVIEW for 英文
上傳時間： 2013-10-14
上傳用戶：shawvi
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上傳時間： 2013-11-15
上傳用戶：努力努力再努力
為滿足無線網(wǎng)絡(luò)技術(shù)具有低功耗、節(jié)點體積小、網(wǎng)絡(luò)容量大、網(wǎng)絡(luò)傳輸可靠等技術(shù)要求，設(shè)計了一種以MSP430單片機和CC2420射頻收發(fā)器組成的無線傳感節(jié)點。通過分析其節(jié)點組成，提出了ZigBee技術(shù)中的幾種網(wǎng)絡(luò)拓撲形式，并研究了ZigBee路由算法。針對不同的傳輸要求形式選用不同的網(wǎng)絡(luò)拓撲形式可以盡大可能地減少系統(tǒng)成本。同時針對不同網(wǎng)絡(luò)選用正確的ZigBee路由算法有效地減少了網(wǎng)絡(luò)能量消耗，提高了系統(tǒng)的可靠性。應(yīng)用試驗表明，采用ZigBee方式通信可以提高傳輸速率且覆蓋范圍大，與傳統(tǒng)的有線通信方式相比可以節(jié)約40%左右的成本。 Abstract: To improve the proposed technical requirements such as low-ower， small nodes， large capacity and reliable network transmission， wireless sensor nodes based on MSP430 MCU and CC2420 RF transceiver were designed. This paper provided network topology of ZigBee technology by analysing the component of the nodes and researched ZigBee routing algorithm. Aiming at different requirements of transmission mode to choose the different network topologies form can most likely reduce the system cost. And aiming at different network to choose the correct ZigBee routing algorithm can effectively reduced the network energy consumption and improved the reliability of the system. Results show that the communication which used ZigBee mode can improve the transmission rate， cover more area and reduce 40% cost compared with traditional wired communications mode.
標(biāo)簽： ZigBee 無線傳感網(wǎng)絡(luò) 協(xié)議研究 路由
上傳時間： 2013-10-09
上傳用戶：robter
Abstract: most hand-held products lack accurate battery-charge monitors ("fuel gauges") because of the misconception that an accurate fuel gauge is difficult to achieve. This article debunks the myths and discusses how to accurately monitor charge at all temperatures, charge and discharge rates, and aging conditions. 無線通信和數(shù)據(jù)在新一代手機和PDA中的融合為再一次的生產(chǎn)力飛躍創(chuàng)造了條件。。隨之而來的將是經(jīng)濟的增長和全新的工作方式，在便攜式計算機領(lǐng)域，PC筆記本曾經(jīng)扮演了類似的開拓者角角。
上傳時間： 2013-10-17
上傳用戶：erkuizhang
Abstract: most hand-held products lack accurate battery-charge monitors ("fuel gauges") because of the misconception that an accurate fuel gauge is difficult to achieve. This article debunks the myths and discusses how to accurately monitor charge at all temperatures, charge and discharge rates, and aging conditions.
上傳時間： 2014-03-18
上傳用戶：wenwiang
This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in general, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.
標(biāo)簽： Algorithms 算法
上傳時間： 2013-11-11
上傳用戶：JamesB
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
Nios II 軟件開發(fā)人員手冊中的緩存和緊耦合存儲器部分 Nios® II embedded processor cores can contain instruction and data caches. This chapter discusses cache-related issues that you need to consider to guarantee that your program executes correctly on the Nios II processor. Fortunately, most software based on the Nios II hardware abstraction layer (HAL) works correctly without any special accommodations for caches. However, some software must manage the cache directly. For code that needs direct control over the cache, the Nios II architecture provides facilities to perform the following actions:
上傳時間： 2013-10-25
上傳用戶：蟲蟲蟲蟲蟲蟲
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上傳時間： 2013-11-11
上傳用戶：csgcd001
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