多遠程二極管溫度傳感器-Design Considerations for pc thermal management Multiple RDTS (remote diode temperature sensing) provides the most accurate method of sensing an IC’s junction temperature. It overcomes thermal gradient and placement issues encountered when trying to place external sensors. PCB component count decreases when using a device that provides multiple inputs.Better temperature sensing improves product performance and reliability. Disk drive data integrity suffers at elevated temperatures. IBM published an article stating that a 5°C rise in operating temperature causes a 15% increase in the drive’s failure rate. The overall performance of a system can be improved by providing a more accurate temperature measurement of the most critical devices allowing them to run just a few degrees hotter.The LM83 directly senses its own temperature and the temperature of three external PN junctions. One is dedicated to the CPU of choice, the other two go to other parts of your system that need thermal monitoring such as the disk drive or graphics chip. The SMBus-compatible LM83 supports SMBus timeout and logic levels. The LM83 has two interrupt outputs; one for user-programmable limits and WATCHDOG capability (INT), the other is a Critical Temperature Alarm output (T_CRIT_A) for system power supply shutdown.
標簽： Considerat Design 遠程 二極管
上傳時間： 2014-12-21
上傳用戶：ljd123456
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上傳時間： 2013-11-15
上傳用戶：努力努力再努力
Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
上傳時間： 2014-01-03
上傳用戶：Huge_Brother
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
上傳時間： 2013-10-10
上傳用戶：geshaowei
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時間： 2013-10-11
上傳用戶：yuchunhai1990
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
上傳時間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
IBIS 模型在做類似板級SI 仿真得到廣泛應用。在做仿真的初級階段，經常對于ibis 模型的描述有些疑問，只知道把模型拿來轉換為軟件所支持的格式或者直接使用，而對于IBIS 模型里面的數據描述什么都不算很明白，因此下面的一些描述是整理出來的一點對于ibis 的基本理解。在此引用很多presention來描述ibis 內容（有的照抄過來，阿彌陀佛，不要說抄襲，只不過習慣信手拈來說明一些問題），僅此向如muranyi 等ibis 先驅者致敬。本文難免有些錯誤或者考慮不周，隨時歡迎進行討論并對其進行修改！IBIS 模型的一些基本概念IBIS 這個詞是Input/Output buffer information specification 的縮寫。本文是基于IBIS ver3.2 所撰寫出來（www.eigroup.org/IBIS/可下載到各種版本spec）,ver4.2增加很多新特性，由于在目前設計中沒用到不予以討論。。。在業界經常會把spice 模型描述為transistor model 是因為它描述很多電路細節問題。而把ibis 模型描述為behavioral model 是因為它并不象spice 模型那樣描述電路的構成，IBIS 模型描述的只不過是電路的一種外在表現，象個黑匣子一樣，輸入什么然后就得到輸出結果，而不需要了解里面驅動或者接收的電路構成。因此有所謂的garbage in, garbage out，ibis 模型的仿真精度依賴于模型的準確度以及考慮的worse case，因此無論你的模型如何精確而考慮的worse case 不周全或者你考慮的worse case 如何周全而模型不精確，都是得不到較好的仿真精度。
上傳時間： 2013-10-16
上傳用戶：zhouli
MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標簽： MAXQUSBJTAGOW 評估板 軟件
上傳時間： 2013-10-24
上傳用戶：teddysha
