IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅動源碼+仿真激勵文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發執行信號 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號 input [15:0] i2c_addr , //I2C器件內地址 input [ 7:0] i2c_data_w , //I2C要寫的數據 output reg [ 7:0] i2c_data_r , //I2C讀出的數據 output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應答標志 0:應答 1:未應答 output reg scl , //I2C的SCL時鐘信號 inout sda , //I2C的SDA信號 //user interface output reg dri_clk //驅動I2C操作的驅動時鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態localparam st_sladdr = 8'b0000_0010; //發送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發送16位字地址localparam st_addr8 = 8'b0000_1000; //發送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數據(8 bit)localparam st_addr_rd = 8'b0010_0000; //發送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數據(8 bit)localparam st_stop = 8'b1000_0000; //結束I2C操作//reg definereg sda_dir ; //I2C數據(SDA)方向控制reg sda_out ; //SDA輸出信號reg st_done ; //狀態結束reg wr_flag ; //寫標志reg [ 6:0] cnt ; //計數reg [ 7:0] cur_state ; //狀態機當前狀態reg [ 7:0] next_state; //狀態機下一狀態reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數據reg [ 7:0] data_wr_t ; //I2C需寫的數據的臨時寄存reg [ 9:0] clk_cnt ; //分頻時
標簽： iic 接口 e2prom at24c64 verilog 驅動 仿真
上傳時間： 2021-11-05
上傳用戶：
使用主流buck降壓芯片設計雙軌電源Creating a Split-Rail Power Supply With a Wide Input Voltage Buck Regulator
標簽： 電源
上傳時間： 2021-11-07
上傳用戶：20125101110
ABSTRACTThe flyback power stage is a popular choice for single and multiple output dc-to-dc converters at powerlevels of 150 Watts or less. Without the output inductor required in buck derived topologies, such as theforward or push-pull converter, the component count and cost are reduced. This application note will reviewthe design procedure for the power stage and control electronics of a flyback converter. In these isolatedconverters, the error signal from the secondary still needs to cross the isolation boundary to achieveregulation. By using the UC3965 Precision Reference with Low Offset Error Amplifier on the secondaryside to drive an optocoupler and the UCC3809 Economy Primary Side Controller on the primary side, asimple and low cost 50 Watt isolated power supply is realized.
標簽： 隔離
上傳時間： 2021-11-24
上傳用戶：kingwide
FPGA讀取OV5640攝像頭數據并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的字符VGA LCD顯示實驗Verilog邏輯源碼Quartus工程文件+文檔說明,通過字符轉換工具將字符轉換為 8 進制 mif 文件存放到單端口的 ROM IP 核中，再從ROM 中把轉換后的數據讀取出來顯示到 VGA 上，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire osd_hs;wire osd_vs;wire osd_de;wire[7:0] osd_r;wire[7:0] osd_g;wire[7:0] osd_b;assign vga_out_hs = osd_hs;assign vga_out_vs = osd_vs;assign vga_out_r = osd_r[7:3]; //discard low bit dataassign vga_out_g = osd_g[7:2]; //discard low bit dataassign vga_out_b = osd_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ));color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b (video_b ));osd_display osd_display_m0( .rst_n (rst_n ), .pclk (video_clk ), .i_hs (video_hs ), .i_vs (video_vs ), .i_de (video_de ), .i_data ({video_r,video_g,video_b} ), .o_hs (osd_hs ), .o_vs (osd_vs ), .o_de (osd_de ), .o_data ({osd_r,osd_g,osd_b} ));endmodule
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的vga顯示測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue );wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;assign vga_out_hs = video_hs;assign vga_out_vs = video_vs;assign vga_out_r = video_r[7:3]; //discard low bit dataassign vga_out_g = video_g[7:2]; //discard low bit dataassign vga_out_b = video_b[7:3]; //discard low bit data//generate video pixel clockvideo_pll video_pll_m0( .inclk0(clk), .c0(video_clk));color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b));endmodule
標簽： fpga vga顯示 verilog quartus
上傳時間： 2021-12-19
上傳用戶：kingwide
FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上傳時間： 2021-12-19
上傳用戶：20125101110
Texas instruments MIPI DSI to eDP converter. Input supports 2 channel, 4 lanes each, up to 1.5GBit/s. Total input bandwidth is 12Gbit/s. Output eDP 1.4 1,2 or 4 lanes up to 5.4Gbit/s. output up to 4096x2304 60fps.
上傳時間： 2021-12-22
上傳用戶：
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
標簽： DDR4
上傳時間： 2022-01-09
上傳用戶：
