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  • Xilinx UltraScale:新一代架構(gòu)滿足您的新一代架構(gòu)需求(EN)

      中文版詳情瀏覽:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The next-Generation Architecture for Your next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    標(biāo)簽: UltraScale Xilinx 架構(gòu)

    上傳時(shí)間: 2013-11-21

    上傳用戶:wxqman

  • 基于Quartus II免費(fèi)IP核的雙端口RAM設(shè)計(jì)實(shí)例

      QuartusII中利用免費(fèi)IP核的設(shè)計(jì)   作者:雷達(dá)室   以設(shè)計(jì)雙端口RAM為例說明。   Step1:打開QuartusII,選擇File—New Project Wizard,創(chuàng)建新工程,出現(xiàn)圖示對(duì)話框,點(diǎn)擊next

    標(biāo)簽: Quartus RAM IP核 雙端口

    上傳時(shí)間: 2013-10-18

    上傳用戶:909000580

  • WP328-FPGA的語音數(shù)據(jù)融合

      The SDI standards are the predominant standards for uncompressed digital videointerfaces in the broadcast studio and video production center. The first SDI standard,SD-SDI, allowed standard-definition digital video to be transported over the coaxial cableinfrastructure initially installed in studios to carry analog video. next, HD-SDI wasto support high-definition video. Finally, dual link HD-SDI and 3G-SDIdoubled the bandwidth of HD-SDI to support 1080p (50 Hz and 60 Hz) and other videoformats requiring more bandwidth than HD-SDI provides.

    標(biāo)簽: FPGA 328 WP 語音

    上傳時(shí)間: 2013-12-08

    上傳用戶:liansi

  • WP312-Xilinx新一代28nm FPGA技術(shù)簡介

    Xilinx next Generation 28 nm FPGA Technology Overview Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.

    標(biāo)簽: Xilinx FPGA 312 WP

    上傳時(shí)間: 2013-12-07

    上傳用戶:bruce

  • 先編寫MFC DLL

    先編寫MFC DLL,打開VC++6.0 => File => New => Project => MFC AppWizzard(dll),在 Project name 里輸入Calc =>next => Finish. 好了,現(xiàn)在你打開Workspace的FileView就可以看到已經(jīng)有Calc.h、Calc.cpp、stdafx.h、stdafx.cpp這4個(gè)文件了.

    標(biāo)簽: MFC DLL 編寫

    上傳時(shí)間: 2013-12-21

    上傳用戶:13681659100

  • 本程序?qū)⒂脩粜畔⒃O(shè)計(jì)成一個(gè)類

    本程序?qū)⒂脩粜畔⒃O(shè)計(jì)成一個(gè)類,使用對(duì)象模擬對(duì) 象數(shù)據(jù)庫,將用戶信息保存到數(shù)據(jù)文件中。并實(shí)現(xiàn)打開 文件,保存文本,添加&刪除用戶信息等功能。 在運(yùn)行的過程中,用戶須先填上自己的姓名、性別 ,然后選擇自己所在省份、城市。點(diǎn)擊“Add”按鈕, 該用戶信息即可添加進(jìn)面板左邊的文本區(qū),點(diǎn)擊 “Delete”時(shí),可刪除該用戶的信息,點(diǎn)擊“Open”可 打開一個(gè)文件,點(diǎn)“Prior”可將該用戶信息上移一行, “next”下移一行,“First”上移至文本區(qū)第一行, “Last”信息下移至最后一行,“Save”保存左邊的文 件為一個(gè)文本文檔。

    標(biāo)簽: 程序 用戶

    上傳時(shí)間: 2015-03-31

    上傳用戶:253189838

  • ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and pri

    ARM下 Implement matrix multiplication of 2 square matrices, with data read from an input file and printed both to the console and to an output file. • Assume a file with correct data (no garbage, characters, etc.). • you must check and provide appropriate execution for 2 extra cases, namely when the matrix size given is either “0” , or when the size is greater than the maximum handled of “5” . In these 2 cases you must implement the following behaviour: o If size = 0, then print a message “Size = 0 is unacceptable” and continue by reading the next size for the next 2 matrices (if not end of file). o If size >5, then print two messages: “Size is too big - unacceptable”. Then read and discard the next (size2 ) integers and continue by reading the next size for the next 2 matrices (if not end of file).

    標(biāo)簽: multiplication Implement matrices matrix

    上傳時(shí)間: 2014-08-30

    上傳用戶:dsgkjgkjg

  • The Audio File Library provides a uniform programming interface to standard digital audio file form

    The Audio File Library provides a uniform programming interface to standard digital audio file formats. This library allows the processing of audio data to and from audio files of many common formats (currently AIFF, AIFF-C, WAVE, next/Sun .snd/.au, IRCAM, AVR, Amiga IFF/8SVX, and NIST SPHERE). The library also supports compression (currently G.711 mu-law and A-law and IMA and MS ADPCM) as well as PCM formats of all flavors (signed and unsigned integer, single- and double-precision floating point).

    標(biāo)簽: programming interface provides standard

    上傳時(shí)間: 2014-12-06

    上傳用戶:a6697238

  • This program demonstrates some function approximation capabilities of a Radial Basis Function Networ

    This program demonstrates some function approximation capabilities of a Radial Basis Function Network. The user supplies a set of training points which represent some "sample" points for some arbitrary curve. next, the user specifies the number of equally spaced gaussian centers and the variance for the network. Using the training samples, the weights multiplying each of the gaussian basis functions arecalculated using the pseudo-inverse (yielding the minimum least-squares solution). The resulting network is then used to approximate the function between the given "sample" points.

    標(biāo)簽: approximation demonstrates capabilities Function

    上傳時(shí)間: 2014-01-01

    上傳用戶:zjf3110

  • The EM algorithm is short for Expectation-Maximization algorithm. It is based on an iterative optimi

    The EM algorithm is short for Expectation-Maximization algorithm. It is based on an iterative optimization of the centers and widths of the kernels. The aim is to optimize the likelihood that the given data points are generated by a mixture of Gaussians. The numbers next to the Gaussians give the relative importance (amplitude) of each component.

    標(biāo)簽: algorithm Expectation-Maximization iterative optimi

    上傳時(shí)間: 2015-06-17

    上傳用戶:獨(dú)孤求源

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