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The LPC1700 Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media Access Controller) designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with Scatter-Gather DMA off-loads many operations from the CPU.
標(biāo)簽：
1700
MIIM
LPC
以太網(wǎng)
上傳時(shí)間：
2013-11-09
上傳用戶：geshaowei
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The PCA9541 is a 2-to-1 I2C-bus master selector designed for high reliability dual masterI2C-bus applications where system operation is required, even when one master fails orthe controller card is removed for maintenance. The two masters (for example, primaryand back-up) are located on separate I2C-buses that connect to the same downstreamI2C-bus slave devices. I2C-bus commands are sent by either I2C-bus master and are usedto select one master at a time. Either master at any time can gain control of the slavedevices if the other master is disabled or removed from the system. The failed master isisolated from the system and will not affect communication between the on-line masterand the slave devices on the downstream I2C-bus.
標(biāo)簽：
master
C-bus
9541
PCA
上傳時(shí)間：
2013-10-09
上傳用戶：3294322651
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The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
標(biāo)簽：
C-bus
9555
SMBu
PCA
上傳時(shí)間：
2013-11-13
上傳用戶：fredguo
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The TL2575 and TL2575HV represent superior alternatives to popular three-terminal linear regulators. Due totheir high efficiency, the devices significantly reduce the size of the heatsink and, in many cases, no heatsink isrequired. Optimized for use with standard series of inductors available from several different manufacturers, theTL2575 and TL2575HV greatly simplify the design of switch-mode power supplies by requiring a minimaladdition of only four to six external components for operation.
標(biāo)簽：
STEP-DOWN
SWITCHING
SIMPLE
1A
上傳時(shí)間：
2013-11-20
上傳用戶：jelenecheung
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The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽：
MULTICHANNEL
5.5
TO
RS
上傳時(shí)間：
2013-10-19
上傳用戶：ddddddd
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PCA9511, PCA9512, PCA9513, PCA9514, PCA9515, PCA9516, PCA9518,P82B96, P82B715Abstract - Philips Semiconductors family of Repeaters, Hubs and Expanders are detailed in this application notethat discusses device operation, maximum cable length and frequency calculations and typical applications.
標(biāo)簽：
REPEATERS
SMBus
255
AN
上傳時(shí)間：
2013-11-21
上傳用戶：wlcaption
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The C500 microcontroller family usually provides only one on-chip synchronous serialchannel (SSC). If a second SSC is required, an emulation of the missing interface mayhelp to avoid an external hardware solution with additional electronic components.The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using optimized SW routines with a performance up to 25KBaud in Slave Mode with half duplex transmission and an overhead less than 60% atSAB C513 with 12 MHz. Due to the implementation in C this performance is not the limitof the chip. A pure implementation in assembler will result in a strong reduction of theCPU load and therefore increase the maximum speed of the interface. In addition,microcontrollers like the SAB C505 will speed up the interface by a factor of two becauseof an optimized architecture compared with the SAB C513.Moreover, this solution lays stress on using as few on-chip hardware resources aspossible. A more excessive consumption of those resources will result in a highermaximum speed of the emulated interface.Due to the restricted performance of an 8 bit microcontroller a pin compatible solution isprovided only; the internal register based programming interface is replaced by a set ofsubroutine calls.The attached source files also contain a test shell, which demonstrates how to exchangeinformation between an on-chip HW-SSC and the emulated SW-SSC via 5 external wiresin different operation modes. It is based on the SAB C513 (Siemens 8 bit microcontroller).A table with load measurements is presented to give an indication for the fraction of CPUperformance required by software for emulating the SSC.
標(biāo)簽：
synchronous
Emulating
serial
上傳時(shí)間：
2014-01-31
上傳用戶：z1191176801
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Presents short and simple I2C software routines that support onlyslave (rather than master or master & slave) operation and an ASMdemonstration program. The slave-only software in this app notecomplements the master mode software presented in AN464, Usingthe 87LPC76X microcontroller as an I2C bus master.
標(biāo)簽：
76X
LPC
IIC
87
上傳時(shí)間：
2013-11-22
上傳用戶：1039312764
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計(jì)算機(jī)應(yīng)用中，有時(shí)需處理的信息不是數(shù)字量，而是一些隨時(shí)間連續(xù)變化的模擬量，甚至是一些非電量，如溫度、壓力、速度等。模擬量的存儲(chǔ)處理困難。首先將非電的模擬信號(hào)變成與之對(duì)應(yīng)的模擬電信號(hào)，這要通過各種傳感器來(lái)完成。計(jì)算機(jī)可處理的信息均是數(shù)字量（電脈沖信號(hào)）1和0，必須把要處理的模擬電量轉(zhuǎn)換成數(shù)字化的電信號(hào)，這需要模擬(Analog)與數(shù)字(Digital)轉(zhuǎn)換電路。數(shù)字到模擬轉(zhuǎn)換:(Digital to Analog Convert, D/A) D/A轉(zhuǎn)換電路是模擬電路加上電子開關(guān)。D/A轉(zhuǎn)換電路的核心是一個(gè)運(yùn)算放大器。運(yùn)算放大器的特性:(Operation Amplifier) K->無(wú)窮大， V和->0 傳遞函數(shù)：V0 = -Vi * R0/Ri Ii->0, I和=If梯形R-2R電阻網(wǎng)絡(luò)D/A轉(zhuǎn)換器Ki受一個(gè)8位二進(jìn)制代碼控制 某位為1，對(duì)應(yīng)開關(guān)K倒向右邊； 某位為0，對(duì)應(yīng)開關(guān)K倒向左邊。Ki不論倒向哪邊，均為接地VA-VH 的電位為： VREF，1/2VREF，..1/128VREFVO= -VREF *（1/2K7+1/4K6+…+1/256K0）V0= -（0-255/256）VREF
8位D/A轉(zhuǎn)換器DAC0830系列器件國(guó)家半導(dǎo)體公司（NS)產(chǎn)品，0830、0831、0832。R-2R梯形電阻網(wǎng)絡(luò)D/A轉(zhuǎn)換器，雙緩沖結(jié)構(gòu)。單電源、低功耗、電流建立時(shí)間1uS。與微計(jì)算機(jī)接口方便。8位D/A轉(zhuǎn)換器DAC0830系列器件ILE： 輸入鎖存允許； WR1#： 加載IN REG； WR2#: 加載DAC REG； XFER#: IN REG傳到DAC REG； Iout1,Iout2: 外接OA輸入； Rfb: 反饋電阻接OA輸出； VREF： 參考電源，控制輸出電壓變化范圍。
標(biāo)簽：
AD轉(zhuǎn)換
上傳時(shí)間：
2013-10-16
上傳用戶：lu2767
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基于USB接口的數(shù)據(jù)采集模塊的設(shè)計(jì)與實(shí)現(xiàn)Design and Implementation of USB-Based Data Acquisition Module路 永 伸(天津科技大學(xué)電子信息與自動(dòng)化學(xué)院，天津300222)摘要文中給出基于USB接口的數(shù)據(jù)采集模塊的設(shè)計(jì)與實(shí)現(xiàn)。硬件設(shè)計(jì)采用以Adpc831與PDIUSBDI2為主的器件進(jìn)行硬件設(shè)計(jì)，采用Windriver開發(fā)USB驅(qū)動(dòng)，并用Visual C十十6.0對(duì)主機(jī)軟件中硬件接口操作部分進(jìn)行動(dòng)態(tài)鏈接庫(kù)封裝。關(guān)鍵詞USB 數(shù)據(jù)采集Adpc831 PDNSBDI2 Windriver動(dòng)態(tài)鏈接庫(kù)Abstract T hed esigna ndim plementaitono fU SB-BasedD ataA cquisiitonM oduleis g iven.Th ec hips oluitonm ainlyw ithA dpc831a ndP DTUSBD12i sused for hardware design. The USB drive is developed場(chǎng)Wmdriver, and the operation on the hardware interface is packaged into Dynamic Link Libraries場(chǎng)Visual C++6.0. Keywords USB DataA cquisition Adttc831 PDfUSBD12 Windriver0 引言US B總 線 是新一代接口總線，最初推出的目的是為了統(tǒng)一取代PC機(jī)的各類外設(shè)接口，迄今經(jīng)歷了1.0,1.1與2.0版本3個(gè)標(biāo)準(zhǔn)。在國(guó)內(nèi)基于USB總線的相關(guān)設(shè)計(jì)與開發(fā)也得到了快速的發(fā)展，很多設(shè)計(jì)者從各自的應(yīng)用領(lǐng)域，用不同方案設(shè)計(jì)出了相應(yīng)的裝置[1,2]。數(shù)據(jù)采集是工業(yè)控制中一個(gè)普遍而重要的環(huán)節(jié)，因此開發(fā)基于USB接口的數(shù)據(jù)采集模塊具有很強(qiáng)的現(xiàn)實(shí)應(yīng)用意義。雖然 US B總線標(biāo)準(zhǔn)已經(jīng)發(fā)展到2.0版本，但由于工業(yè)控制現(xiàn)場(chǎng)干擾信號(hào)的情況比較復(fù)雜，高速數(shù)據(jù)傳輸?shù)目煽啃圆蝗菀妆槐ＷC，并且很多場(chǎng)合對(duì)數(shù)據(jù)采集的實(shí)時(shí)性要求并不高，開發(fā)2.0標(biāo)準(zhǔn)產(chǎn)品的成本又較1.1標(biāo)準(zhǔn)產(chǎn)品高，所以筆者認(rèn)為，在工業(yè)控制領(lǐng)域，目前開發(fā)基于USB總線1.1標(biāo)準(zhǔn)實(shí)現(xiàn)的數(shù)據(jù)采集模塊的實(shí)用意義大于相應(yīng)2.0標(biāo)準(zhǔn)模塊。
標(biāo)簽：
USB
接口
數(shù)據(jù)采集模塊
上傳時(shí)間：
2013-10-23
上傳用戶：q3290766
