PCI-PCI 橋啟動(dòng)時(shí)，一般需要從EEPROM 預(yù)讀取配置數(shù)據(jù)。更改EEPROM中的數(shù)據(jù)一般需要專用的燒結(jié)器，這給調(diào)試過(guò)程帶來(lái)不便。尤其是采用表貼封裝的EEPROM。本文以Intel 公司的Dec21554PCI-PCI 橋?yàn)槔榻B一種在線讀寫EEPROM 的方法。EEPROM選用的是ATMEL 公司生產(chǎn)的AT93LC66，4Kbit，按512×8bit 組織。
上傳時(shí)間： 2013-11-08
上傳用戶：trepb001
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2014-01-24
上傳用戶：s363994250
PCI-E是一種高速傳輸總線形式。
標(biāo)簽： PCI-E 8622 數(shù)據(jù)采集卡
上傳時(shí)間： 2013-12-18
上傳用戶：宋桃子
PCI-1734快速安裝使用手冊(cè)PCI-1734快速安裝使用手冊(cè)PCI-1734快速安裝使用手冊(cè)PCI-1734快速安裝使用手冊(cè)PCI-1734快速安裝使用手冊(cè)PCI-1734快速安裝使用手冊(cè)PCI-1734快速安裝使用手冊(cè)
上傳時(shí)間： 2013-10-22
上傳用戶：ssz1990
本文介紹一種基于PCI Express 總線的高速數(shù)據(jù)采集卡的設(shè)計(jì)方案及功能實(shí)現(xiàn)。給出系統(tǒng)的基本結(jié)構(gòu)及單元組成，重點(diǎn)闡述系統(tǒng)硬件設(shè)計(jì)的關(guān)鍵技術(shù)和本地總線的控制邏輯，詳細(xì)探討了基于DriverWorks 的設(shè)備驅(qū)動(dòng)程序的開發(fā)以及上層應(yīng)用軟件的設(shè)計(jì)。該系統(tǒng)通過(guò)實(shí)踐驗(yàn)證，可用于衛(wèi)星下行高速數(shù)據(jù)的接收并可適用于其他高速數(shù)據(jù)采集與處理系統(tǒng)。關(guān)鍵詞：PCI Express 總線 PCIE PEX8311 DMA 板卡驅(qū)動(dòng) 隨著空間科學(xué)和空間電子學(xué)技術(shù)的飛速發(fā)展，空間科學(xué)實(shí)驗(yàn)的種類和數(shù)量以及科學(xué)實(shí)驗(yàn)所產(chǎn)生的數(shù)據(jù)量不斷增加。為了使地面接收處理系統(tǒng)能夠?qū)崟r(shí)處理和顯示科學(xué)圖像數(shù)據(jù)，必須要設(shè)計(jì)出新的地面數(shù)據(jù)接收處理系統(tǒng)，實(shí)現(xiàn)大量高速數(shù)據(jù)的正確接收采集、處理以及存儲(chǔ)。為了滿足地面系統(tǒng)的要求，并為以后的計(jì)算機(jī)系統(tǒng)升級(jí)提供更廣闊的空間，本系統(tǒng)擬采用第三代I/O 互連技術(shù)PCI Express（簡(jiǎn)稱PCI-E）作為本數(shù)據(jù)采集卡的進(jìn)機(jī)總線形式。本文通過(guò)對(duì)PCI-E 總線專用接口芯片PLX 公司的PEX8311 性能分析，特別是對(duì)突發(fā)讀、寫和DMA讀操作的時(shí)序研究，設(shè)計(jì)出本地總線的可編程控制邏輯，并詳細(xì)討論了整個(gè)PCI-E 高速數(shù)據(jù)采集卡的硬件設(shè)計(jì)方案，以及WDM 驅(qū)動(dòng)程序和上層應(yīng)用程序的設(shè)計(jì)方法。
標(biāo)簽： Express PCI 總線 卡的設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：tianyi996
瀏覽所有的PCI設(shè)備
上傳時(shí)間： 2015-01-03
上傳用戶：zsjinju
一個(gè)通過(guò)PCI卡向LED屏發(fā)送股票實(shí)時(shí)行情的系統(tǒng)
上傳時(shí)間： 2015-01-04
上傳用戶：498732662
PCI接口的Verilog源代碼
上傳時(shí)間： 2013-12-28
上傳用戶：l254587896
pci驅(qū)動(dòng)程序的源代碼
標(biāo)簽： pci 驅(qū)動(dòng)程序 源代碼
上傳時(shí)間： 2015-01-12
上傳用戶：ljmwh2000
PCI接口的PCMCIA轉(zhuǎn)界卡的2000驅(qū)動(dòng)，解決2000不支持存儲(chǔ)卡問題
上傳時(shí)間： 2014-01-17
上傳用戶：王楚楚
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