ACPCI系列的產品就是專為工控機和臺式機及其他電腦工程項目和測試調試設計的。和計算機的連接接口是通用的PCI接口，ACPCI是南京來可電子根據多年的CAN總線工程應用經驗總結而成的，力求在CAN總線的兼容性、穩定性和標準性上做到最好，ACPCI的單通道發送速度最高大于5000幀/秒，單通道接收速度最高大于7000幀/秒。總線2500V DC-DC隔離，總線接口防雷擊浪涌保護，配套有免費的測試軟件Adawin CANTest，方便對卡和客戶的CAN應用系統進行測試。
上傳時間： 2013-11-08
上傳用戶：born2007
通過對刀片服務器基本概念、主要組成以及內部架構的分析和研究，針對刀片與主板之間的高速通信需求，采用PCI總線作為系統的數據通信協議，給出了PCI局部總線的詳細分析和設計流程，以及系統所采用的"PCI＋FPGA＋FLASH"方案的具體實現方法和步驟，最后給出了實際的測試驗證結果，相關結論，對設計PCI通信系統具有較強的借鑒意義。
上傳時間： 2013-10-30
上傳用戶：liuxinyu2016
VxWorks是WindRiver（風河）公司開發的嵌入式實時操作系統（RTOS），由于它的高實時性，所以廣泛地應用于軍事、工業控制、通信等領域；分析了VxWorks下PCI總線多功能數據采集卡的實現方法；以ADLINK的PCI7396數據采集卡為例，介紹PCI總線設備的配置空間，包括它的結構及訪問方法，重點介紹PCI總線設備在VxWorks下驅動程序的開發步驟及編程要點，并對開發過程中的關鍵部分給予代碼說明；在某綜合控制系統中，開發的驅動程序運行穩定、可靠。
上傳時間： 2013-11-02
上傳用戶：masochism
利用PCI專用接口芯片PCI9052和DEI1016 429總線收發芯片設計了ARINC429接口卡，采用DSP作為主控CPU完成數據自動處理，用雙口RAM完成DSP與PCI總線數據交換。實驗表明：所設計的接口卡傳輸效率高，可靠性好，開發簡單。
上傳時間： 2014-12-30
上傳用戶：love1314
PCI總線是目前最為流行的一種局部性總線 通過對PCI總線一些典型功能的分析以及時序的闡述，利用VetilogHDL設計了一個將非PCI功能設備轉接到PC1總線上的IP Core 同時，通過在ModeISim SE PLUS 6．0 上運行測試程序模塊，得到了理想的仿真數據波形，從軟件上證明了功能的實現。
上傳時間： 2014-12-30
上傳用戶：himbly
The PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.
上傳時間： 2013-11-01
上傳用戶：KSLYZ
作為一種獨立于處理器的局部總線,PCI非常適用于網絡適配器、硬盤驅動器、全動態視頻卡、圖形卡及各類高速外設。據稱,目前有90%的Pentium處理器采用PCI做為系統總線。
上傳時間： 2013-11-07
上傳用戶：liaocs77
PCI Express是由Intel，Dell，Compaq，IBM，Microsoft等PCI SIG聯合成立的Arapahoe Work Group共同草擬并推舉成取代PCI總線標準的下一代標準。PCI Express利用串行的連接特點能輕松將數據傳輸速度提到一個很高的頻率，達到遠遠超出PCI總線的傳輸速率。一個PCI Express連接可以被配置成x1，x2，x4，x8，x12，x16和x32的數據帶寬。x1的通道能實現單向312.5 MB／s（2.5 Gb／s）的傳輸速率。Xilinx公司的Virtex5系列FPGA芯片內嵌PCI-ExpressEndpoint Block硬核，為實現單片可配置PCI-Express總線解決方案提供了可能?！ ”疚脑谘芯縋CI-Express接口協議和PCI-Express Endpoint Block硬核的基礎上，使用Virtex5LXT50 FPGA芯片設計PCI Express接口硬件電路，實現PCI-Express數據傳輸
上傳時間： 2013-12-27
上傳用戶：wtrl
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
上傳時間： 2013-11-14
上傳用戶：zoudejile
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
