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questions

  • Solution to Analog questions.

    Solution to Analog questions.

    標(biāo)簽: questions Solution Analog to

    上傳時(shí)間: 2013-12-19

    上傳用戶(hù):笨小孩

  • 在單端應(yīng)用中采用差分I/O放大器

      Recent advances in low voltage silicon germaniumand BiCMOS processes have allowed the design andproduction of very high speed amplifi ers. Because theprocesses are low voltage, most of the amplifi er designshave incorporated differential inputs and outputs to regainand maximize total output signal swing. Since many lowvoltageapplications are single-ended, the questions arise,“How can I use a differential I/O amplifi er in a single-endedapplication?” and “What are the implications of suchuse?” This Design Note addresses some of the practicalimplications and demonstrates specifi c single-endedapplications using the 3GHz gain-bandwidth LTC6406differential I/O amplifi er.

    標(biāo)簽: 單端應(yīng)用 差分 放大器

    上傳時(shí)間: 2013-11-23

    上傳用戶(hù):rocketrevenge

  • PCI ExpressTM Architecture

    PCI ExpressTM Architecture Add-in Card Compliance Checklist for the PCI Express Base 1.0a SpecificationThe PCI Special Interest Group disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI Special Interest Group make a commitment to update the information contained herein.Contact the PCI Special Interest Group office to obtain the latest revision of this checklistquestions regarding the ths document or membership in the PCI Special Interest Group may be forwarded tPCI Special Interest Group5440 SW Westgate Drive #217Portland, OR 97221Phone: 503-291-2569Fax: 503-297-1090 DISCLAIMERThis document is provided "as is" with no warranties whatsoever, including any warranty of merchantability, noninfringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample.  The PCI SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification.  No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein.

    標(biāo)簽: Architecture ExpressTM PCI

    上傳時(shí)間: 2013-11-03

    上傳用戶(hù):gy592333

  • PCIe Trusted Configuration Spa

    TCS ECN Background & Key TermsTrust Issues with PCIe PlatformsTCS ECN DetailsTrusted Config Space and TCS TransactionsTrusted Config Access Mech (TCAM)Standard vs Trusted Config AccessNew Capability StructuresTCS Support in Root Ports, Switches, & BridgesTCS “Does not…” ListExample Trusted Computing PlatformRevisiting the Trust IssuesKey Takeaways/Call to Actionquestions

    標(biāo)簽: Configuration Trusted PCIe Spa

    上傳時(shí)間: 2013-11-21

    上傳用戶(hù):hsfei8

  • 智能電網(wǎng)安全性

    Abstract: The rapid build out of today's smart grid raises a number of security questions. In this article,we review two recent well-documented security breaches and a report of a security gap. These situationsinclude a 2009 smart-meter hack in Puerto Rico; a 2012 password discovery in grid distributionequipment; and insecure storage of a private key in distribution automation equipment. For each of theseattacks, we examine the breach, the potential threat, and secure silicon methods that, as part of acomplete security strategy, can help thwart the attacks.

    標(biāo)簽: 智能電網(wǎng) 安全性

    上傳時(shí)間: 2013-10-27

    上傳用戶(hù):tecman

  • H.264高清編解碼器的片上系統(tǒng)MG3500

    MG3500SoC是支持H.264高清編解碼器的片上系統(tǒng),內(nèi)部集成一個(gè)嵌入式ARM926處理器,支持高清H.264編解碼、MPEG鄄2解碼和JPEG編解碼。介紹了MG3500SoC的主要性能特點(diǎn)、引腳排列、主要接口功能及在DVR上的應(yīng)用,以及MG3500SoC及其周?chē)骷挠布O(shè)計(jì),提出了在設(shè)計(jì)中應(yīng)注意的問(wèn)題。 Abstract:  The MG3500System-on-Chip(SoC)is high definition(HD)H.264codec,including ARM926-EJ processor,H.264encoder/decoder,MPEG2decoder and JPEG/MJPEG encoder/decoder.The features,pin assignments,interfaces and the typical application of MG3500in DVR are introduced in this paper.The application hardware circuit between the MG3500SoC and peripheral device are given,the questions which the syetem design needs to pay attention are explained.

    標(biāo)簽: 3500 264 MG 編解碼器

    上傳時(shí)間: 2013-11-12

    上傳用戶(hù):elinuxzj

  • CPLD和FPGA設(shè)計(jì)介紹

    Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.

    標(biāo)簽: CPLD FPGA

    上傳時(shí)間: 2013-10-29

    上傳用戶(hù):lixqiang

  • 克服了正交頻分復(fù)用(OFDM)和IEEE 1901.2智能電網(wǎng)通信的挑戰(zhàn)

    Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.

    標(biāo)簽: 1901.2 OFDM IEEE 正交頻分復(fù)用

    上傳時(shí)間: 2013-10-18

    上傳用戶(hù):myworkpost

  • 半導(dǎo)體制造技術(shù)_英文教程

    The correct answer for each test bank question is highlighted in bold. Test bank questions are based on the end-of-chapter questions. If a student studies the end-of-chapter questions (which are linked to the italicized words in each chapter), then they will be successful on the test bank questions.

    標(biāo)簽: 半導(dǎo)體制造技術(shù) 英文 教程

    上傳時(shí)間: 2014-12-31

    上傳用戶(hù):旗魚(yú)旗魚(yú)

  • CPLD和FPGA設(shè)計(jì)介紹

    Field Programmable Gate Arrays (FPGAs) are becoming a critical part of every system design. Many vendors offer many different architectures and processes. Which one is right for your design? How do you design one of these so that it works correctly and functions as you expect in your entire system? These are the questions that this paper sets out to answer.

    標(biāo)簽: CPLD FPGA

    上傳時(shí)間: 2013-10-22

    上傳用戶(hù):lmq0059

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