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  • C in a Nutshell is the perfect companion to K&R, and destined to be the most reached-for reference o

    C in a Nutshell is the perfect companion to K&R, and destined to be the most reached-for reference on your desk.

    標簽: reached-for companion the reference

    上傳時間: 2015-07-26

    上傳用戶:kr770906

  • well reached up for date

    well reached up for date

    標簽: reached well date for

    上傳時間: 2014-11-18

    上傳用戶:牧羊人8920

  • Design Safe Verilog State Machine(Synplicity)

      One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

    標簽: Synplicity Machine Verilog Design

    上傳時間: 2013-10-23

    上傳用戶:司令部正軍級

  • Creating Safe State Machines(Mentor)

      Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.

    標簽: Creating Machines Mentor State

    上傳時間: 2013-10-08

    上傳用戶:wangzhen1990

  • 基于雙ATmega128的安檢力學試驗機設計

    針對當前安檢力學試驗機所能完成的試驗種類單一、自動化程度低等問題,提出一種以ATmega128單片機為核心控制器的安檢力學試驗機的設計。詳細闡述了該安檢力學試驗機各個組成部分的設計原理和方案,并且給出了各部分的軟件設計思想和操作流程。經過大量測試試驗表明:設計的安檢力學試驗機可以完成多達十余種的力學安檢試驗,完全符合相關國家標準,并且具有數據采集精度高、傳輸速度快、操作安全簡便等特點,實現了安檢設備的多功能化、數字化和自動化。 Abstract:  Currently, many mechanical security testing machines have only one function. The degree of automation of them is low. To solve those problems, a new kind of mechanical security testing machine, using ATmega128 micro-controller as its core controller, has been advanced. It describes the components of the machine. The principles and the scheme in the designing processes are presented in detail, and the software architecture and the operation processes of each part are given. After having done many testing, we have reached the following conclusions: the mechanical security testing machine presented can do over ten mechanical security tests complying with related national standards. It has high data acquisition accuracy and high transmission speed. The operation of the machine is simple and safe. In general, this machine is a multi-functional, highly automatic, digitalized security testing device.

    標簽: ATmega 128 安檢 試驗機

    上傳時間: 2013-11-05

    上傳用戶:a67818601

  • C語言函數大全(語法著色版)

        C語言函數大全,已包含絕大部分的函數。每個函數包含函數名,功能,用法,舉例,內容詳盡。希望對大家有所幫助~~   函數名: abort   功 能: 異常終止一個進程   用 法: void abort(void);   程序例:   #include   #include   int main(void)   {   printf("Calling abort()\n");   abort();   return 0; /* This is never reached */   }   函數名: abs   功 能: 求整數的絕對值   用 法: int abs(int i);   程序例:   #include   #include   int main(void)   {   int number = -1234;   printf("number: %d absolute value: %d\n", number, abs(number));   return 0;   }

    標簽: C語言 函數

    上傳時間: 2013-12-06

    上傳用戶:feifei0302

  • Design Safe Verilog State Machine(Synplicity)

      One of the strengths of Synplify is the Finite State Machine compiler. This is a powerfulfeature that not only has the ability to automatically detect state machines in the sourcecode, and implement them with either sequential, gray, or one-hot encoding. But alsoperform a reachability analysis to determine all the states that could possibly bereached, and optimize away all states and transition logic that can not be reached.Thus, producing a highly optimal final implementation of the state machine.

    標簽: Synplicity Machine Verilog Design

    上傳時間: 2013-10-20

    上傳用戶:蒼山觀海

  • Creating Safe State Machines(Mentor)

      Finite state machines are widely used in digital circuit designs. Generally, when designing a state machine using an HDL, the synthesis tools will optimize away all states that cannot be reached and generate a highly optimized circuit. Sometimes, however, the optimization is not acceptable. For example, if the circuit powers up in an invalid state, or the circuit is in an extreme working environment and a glitch sends it into an undesired state, the circuit may never get back to its normal operating condition.

    標簽: Creating Machines Mentor State

    上傳時間: 2013-11-02

    上傳用戶:xauthu

  • C++ Template Metaprogramming sheds light on the most powerful idioms of today s C++, at long last de

    C++ Template Metaprogramming sheds light on the most powerful idioms of today s C++, at long last delivering practical metaprogramming tools and techniques into the hands of the everyday programmer. A metaprogram is a program that generates or manipulates program code. Ever since generic programming was introduced to C++, programmers have discovered myriad "template tricks" for manipulating programs as they are compiled, effectively eliminating the barrier between program and metaprogram. While excitement among C++ experts about these capabilities has reached the community at large, their practical application remains out of reach for most programmers. This book explains what metaprogramming is and how it is best used. It provides the foundation you ll need to use the template metaprogramming effectively in your own work.

    標簽: Metaprogramming Template powerful idioms

    上傳時間: 2013-11-30

    上傳用戶:aix008

  • Ink Blotting One method for escaping from a maze is via ‘ink-blotting’. In this method your startin

    Ink Blotting One method for escaping from a maze is via ‘ink-blotting’. In this method your starting square is marked with the number ‘1’. All free, valid squares north, south, east and west around the number ‘1‘ are marked with a number ‘2’. In the next step, all free, valid squares around the two are marked with a ‘3’ and the process is repeated iteratively until :  The exit is found (a free square other than the starting position is reached on the very edge of the maze), or,  No more free squares are available, and hence no exit is possible.

    標簽: method ink-blotting Blotting escaping

    上傳時間: 2014-12-03

    上傳用戶:123啊

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