Readers can pick up this book and become familiar with C++ in a short time. Stan has taken a very broad and complicated topic and reduced it to the essentials that budding C++ programmers need to know to write real programs. His case study is effective and provides a familiar thread throughout the book.
The Network Security Response Framework (NSRF) allows for testing different computer security response engines and methodologies. It supports simulated and real: Intrusion Detection Systems (sensors), Attacks, and Responses.
As of UnZip 5.42, this source has been removed from Info-ZIP s
UnZip source distribution because of its conflicting copyright.
There are no plans to ever rewrite this code from scratch,
because the unreduce algorithm was never used in the "real" world.
zemax源碼：
This DLL models a standard ZEMAX surface type, either plane, sphere, or conic
The surface also demonstrates a user-defined apodization filter
The filter is defined as part of the real ray trace, case 5
The filter can be used at the stop to produce x-y Gaussian apodization similar to the Gaussian pupil apodization in ZEMAX but separate in x and y.
The amplitude apodization is of the form EXP[-(Gx(x/R)^2 + Gy(y/R)^2)]
The transmission is of the form EXP[-2(Gx(x/R)^2 + Gy(y/R)^2)]
where
x^2 + y^2 = r^2
R = semi-diameter
The tranmitted intensity is maximum in the center.
T is set to 0 if semi-diameter < 1e-10 to avoid division by zero.
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關(guān)于FPGA流水線設(shè)計的論文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.
Individual files are available in the following links:
Bessjy -- Bessel functions Jn and Yn for real argument and integer or real order.
Bessik -- Modified Bessel function In and Kn for real argument and integer or real order.
CBessjy -- Bessel functions Jv and Yv for real or complex arguments and real order.
CBessik -- Modified Bessel functions Iv and Kv for complex arguments and real order.
A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adjustable parameters allow discrimination of "real" signal peaks from noise and background.
A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adjustable parameters allow discrimination of "real" signal peaks from noise and background. Determines the position, height, and width of each peak by least-squares curve-fitting.
The Spectral Toolkit is a C++ spectral transform library written by Rodney James and Chuck Panaccione while at the National Center for Atmospheric Research between 2002 and 2005. The library contains a functional subset of FFTPACK and SPHEREPACK, including real and complex FFTs in 1-3 dimensions, and a spherical harmonic transform. Multithreading is supported through POSIX threads for the multidimensional transforms. This reference guide provides details of the public interface as well as the internal implementation of the library.
