數字秒表的設計，reset為歸零設置，start為重新計時設置
標簽： 數字秒表
上傳時間： 2013-12-12
上傳用戶：xieguodong1234
D169 Demo - DMA0 Repeated Burst to-from RAM, Software Trigger Description A 32 byte block from 220h-240h is transfered to 240h-260h using DMA0 in a burst block using software DMAREQ trigger. After each transfer, source, destination and DMA size are reset to inital software setting because DMA transfer mode 5 is used. P1.0 is toggled durring DMA transfer only for demonstration purposes. ** RAM location 0x220 - 0x260 used - always make sure no compiler conflict ** ACLK= n/a, MCLK= SMCLK= default DCO ~ 800k
標簽： Description Repeated Software to-from
上傳時間： 2014-01-09
上傳用戶：thinode
CRC碼產生器與校驗器程序 Features ： Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset
標簽： polynomial Features Executes clock
上傳時間： 2013-12-18
上傳用戶：Ants
The VGA example generates a 320x240 diffusion-limited-aggregation (DLA) on Altera DE2 board. A DLA is a clump formed by sticky particles adhering to an existing structure. In this design, we start with one pixel at the center of the screen and allow a random walker to bounce around the screen until it hits the pixel at the center. It then sticks and a new walker is started randomly at one of the 4 corners of the screen. The random number generators for x and y steps are XOR feedback shift registers (see also Hamblen, Appendix A). The VGA driver, PLL, and reset controller from the DE2 CDROM are necessary to compile this example. Note that you must push KEY0 to start the state machine.
標簽： diffusion-limited-aggregation DLA generates 320x240
上傳時間： 2014-01-16
上傳用戶：225588
linux下同一個進程中多個定時器實現。簡單描述下定時器模塊的實現，有一個manager單例類保存所有CTimer對象，開啟一線程運行延遲函數，每次延遲間隔到，掃描保存CTimer的容器，對每個CTimer對象執行減少時間操作，減少到0則執行回調函數。對一次性CTimer，超時則從容器中刪除，循環型的將間隔時間重置，不從容器中移除。 CTimer的start執行將對象插入到manager容器中操作；stop執行將對象從manager容器中刪除的操作；reset執行先刪除，重置間隔，然后再放到容器中，reset不改變CTimer的定時器類型屬性。 代碼來源于CppExplore，感謝博客主的共享。
上傳時間： 2017-01-03
上傳用戶：daguda
/* 線路圖 89C51 T6963C -------- | 8 P1.0-1.7|=========== D0-7 | P3.0|----------- /RD P3.1|----------- /WR P3.2|----------- C/D | -- /CE | | | --- P3.3|----------- /reset | VCC--- /HALT -------- */
上傳時間： 2013-12-20
上傳用戶：集美慧
DESCRIPTION The DCP0105 family is a series of high efficiency, 5V input isolated DC/DC converters. In addition to 1W nominal galvanically isolated output power capability, the range of DC/DCs are also fully synchronizable. The devices feature thermal shutdown, and overload protection is implemented via watchdog circuitry. Advanced power-on reset techniques give superior reset performance and the devices will start into any capacitive load up to full power output. The DCP0105 family is implemented in standard- molded IC packaging, giving outlines suitable for high volume assembly.
標簽： DESCRIPTION efficiency converters isolated
上傳時間： 2013-11-28
上傳用戶：CHENKAI
偽隨機序列發生器的vhdl算法 設計一個偽隨機序列發生器，采用的生成多項式為1+X^3+X^7。要求具有一個reset端和兩個控制端來調整寄存器初值（程序中設定好四種非零初值可選）
上傳時間： 2014-12-03
上傳用戶：小寶愛考拉
管腳號 管腳名稱 LEVER 管腳功能描述 1 VSS 0V 電源地 2 VDD 5.0V 電源電壓 3 VEE 5.0V~(-13V) 液晶顯示器驅動電壓 4 D/I H/L D/I=“H”,表示DB7~DB0為顯示數據 D/I=“L”,表示DB7~DB0為顯示指令數據 5 R/W H/L R/W=“H”,E=“H”,數據被讀到DB7~DB0 R/W=“L”,E=“H→L”, DB7~DB0的數據被寫到IR或DR 6 E H/L 使能信號：R/W=“L”,E信號下降沿鎖存DB7~DB0 R/W=“H”,E=“H” DRAM數據讀到DB7~DB0 7 DB0 H/L 數據線 8 DB1 H/L 數據線 9 DB2 H/L 數據線 10 DB3 H/L 數據線 11 DB4 H/L 數據線 12 DB5 H/L 數據線 13 DB6 H/L 數據線 14 DB7 H/L 數據線 15 CS1 L （19264A) 選擇IC1,即（左）64列 16 reset L 復位控制信號，RST=0有效 17 CS2 L （19264A) 選擇IC2,即（中）64列 18 CS3 L （19264A) 選擇IC3,即（右）64列 19 V0 -9V Negative Voltage for LCD driving 20 LED+ +5.0V The LED supply
上傳時間： 2014-01-01
上傳用戶：541657925
The MINI2440 is an effecient ARM9 development board with a comprehensive price, it characterizes simple method and high performance-price ratio. Based on the Samsung S3C2440 microprocessor, it embodies professional stable CPU core power source chip and reset chip to ensure the stability of the system operation. The PCB on the MINI2440 board is designed to be 4-layers board, adopting the ENIG technology and professional equal-length wiring to ensure the completeness of the signals of the key signal wires and manufactured and released under stringent quality control plans. With the help of this detailed manual, users are supposed to become proficient in the development process of embedded Linux and WinCE operating system, they are supposed to get the foundation, so long as they have obtained the basic and necessary knowledge about the C language, in two weeks.
標簽： comprehensive characterizes development effecient
上傳時間： 2013-12-18
上傳用戶：csgcd001
