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scaling pictures.doc
上傳時(shí)間： 2017-05-17
上傳用戶：thuyenvinh
The aip file contains few Matlab routines for 1D line scan analysis, 1D scaling, 2D scaling, image brightness or contrast variation routine and rouitne for finding area between zero cossings of 1D times series.
標(biāo)簽： scaling contains analysis routines
上傳時(shí)間： 2014-01-19
上傳用戶：xmsmh
Resource scaling Effects on MPP Performance: The STAP Benchmark Implications
標(biāo)簽： Implications Performance Benchmark Resource
上傳時(shí)間： 2017-06-14
上傳用戶：star_in_rain
使用DM642 來(lái)進(jìn)行scaling 有說明檔
上傳時(shí)間： 2014-01-24
上傳用戶：sxdtlqqjl
Abstract: A digital RF modulator, an integrated solution that satisfies stringent DOCSIS RF-performancerequirements, takes advantage of modern technologies like high-performance wideband digital-to-analogconversion and CMOS technology scaling. This application note describes the concept and advantages ofa digital quadrature amplitude modulation (QAM) modulator that uses the direct-RF architecture to enablea cable access platform (CCAP) system.
標(biāo)簽： 集成 數(shù)字RF 調(diào)制器 方案
上傳時(shí)間： 2013-10-20
上傳用戶：drink！
Abstract: Mechanical misalignment and scaling factors lead to a mismatch between the values coming from a touchscreen panel (as translated by a touch screen controller) and the display (typically an LCD) on which the touch screenpanel is mounted. This tutorial discusses how to calibrate the touch screen panel to match the display.
標(biāo)簽： 校準(zhǔn) 觸摸屏 系統(tǒng)研究
上傳時(shí)間： 2013-10-21
上傳用戶：euroford
Analog Inputs and Outputs in an S7 PLC are represented in the PLC as a 16-bit integer. Over the nominal span of the analog input or output, the value of this integer will range between - 27648 and +27648. However, it is easier to use the analog values if they are scaled to the same units and ranges as the process being controlled. This applications tip describes methods for scaling analog values to and from engineering units.
上傳時(shí)間： 2013-11-17
上傳用戶：3294322651
為了解決磁放大器性能測(cè)試過程中，需要對(duì)其供給不同數(shù)值恒定電流的問題，設(shè)計(jì)了一種基于DAC7512和單片機(jī)的數(shù)控恒流源系統(tǒng)。該系統(tǒng)采用AT89C51作為主控器件，將計(jì)算機(jī)發(fā)送的電流控制字命令轉(zhuǎn)換為D/A轉(zhuǎn)換器控制字，通過模擬SPI通信接口，寫D/A控制字到DAC7512，從而控制其輸出相應(yīng)數(shù)字電壓值，經(jīng)差動(dòng)縮放電路、電壓/電路變換電路和功率驅(qū)動(dòng)電路，最后輸出恒定電流。實(shí)驗(yàn)結(jié)果表明，恒流源輸出電流調(diào)節(jié)范圍為-45~+45 mA、精度為±0.1 mA，分辨率達(dá)0.024 4 mA，具有應(yīng)用靈活，外圍電路簡(jiǎn)單，可靠性高的特點(diǎn)。該數(shù)控直流恒流源也可為相關(guān)產(chǎn)品的測(cè)試系統(tǒng)研發(fā)提供參考。 Abstract: In order to solve the need to supply different values constant current for the magnetic amplifier in testing process， numerical control constant current source system was designed based on DAC7512 chip and microcontroller technology. The system used the AT89C51 as the main chip， which can convert the current control word from computer into to D/A control words. And the system wrote D/A control word into the DAC7512 chip to control the output voltage value by the SPI communication interface， which can output corresponding constant current figures by scaling circuit， the V/I converter and power drive circuit. Experimental results show that the current source output current adjustment range is -45~+45mA， accuracy is ± 0.1mA， and resolution ratio is 0.024 4mA
標(biāo)簽： 7512 DAC 數(shù)控直流 恒流源
上傳時(shí)間： 2014-12-27
上傳用戶：invtnewer
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時(shí)間： 2013-10-11
上傳用戶：yuchunhai1990
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