這一實驗性的“餐館系統”是一個很典型商業應用，但并不復雜。歸根結底，就實現5個功能：1）增加一個新的預約（涉及數據庫中的一個insert操作），2）刪除一個被選中的預約（delete操作），3）在一個已有預約上記錄到達時間（提前預約的顧客來吃飯了）（對應update操作），4）更改分配給一個預約的餐桌（update操作），5）顯示指定日期內所有已有的預約（select操作）。從數據庫的角度來看，要實現這些功能不難。在我們的樣板系統中，在運行時主要通過以下對象的合作，實現上述功能。
上傳時間： 2018-11-02
上傳用戶：jack110
Introduction jSMPP is a java implementation (SMPP API) of the SMPP protocol (currently supports SMPP v3.4). It provides interfaces to communicate with a Message Center or an ESME (External Short Message Entity) and is able to handle traffic of 3000-5000 messages per second. jSMPP is not a high-level library. People looking for a quick way to get started with SMPP may be better of using an abstraction layer such as the Apache Camel SMPP component: http://camel.apache.org/smpp.html Travis-CI status: History The project started on Google Code: http://code.google.com/p/jsmpp/ It was maintained by uudashr on Github until 2013. It is now a community project maintained at http://jsmpp.org Release procedure mvn deploy -DperformRelease=true -Durl=https://oss.sonatype.org/service/local/staging/deploy/maven2/ -DrepositoryId=sonatype-nexus-staging -Dgpg.passphrase=<yourpassphrase> log in here: https://oss.sonatype.org click the 'Staging Repositories' link select the repository and click close select the repository and click release License Copyright (C) 2007-2013, Nuruddin Ashr uudashr@gmail.com Copyright (C) 2012-2013, Denis Kostousov denis.kostousov@gmail.com Copyright (C) 2014, Daniel Pocock http://danielpocock.com Copyright (C) 2016, Pim Moerenhout pim.moerenhout@gmail.com This project is licensed under the Apache Software License 2.0.
上傳時間： 2019-01-25
上傳用戶：dragon_longer
The past decade has seen an explosion of machine learning research and appli- cations; especially, deep learning methods have enabled key advances in many applicationdomains,suchas computervision,speechprocessing,andgameplaying. However, the performance of many machine learning methods is very sensitive to a plethora of design decisions, which constitutes a considerable barrier for new users. This is particularly true in the booming field of deep learning, where human engineers need to select the right neural architectures, training procedures, regularization methods, and hyperparameters of all of these components in order to make their networks do what they are supposed to do with sufficient performance. This process has to be repeated for every application. Even experts are often left with tedious episodes of trial and error until they identify a good set of choices for a particular dataset.
標簽： Auto-Machine-Learning-Methods-Sys tems-Challenges
上傳時間： 2020-06-10
上傳用戶：shancjb
%this is an example demonstrating the Radial Basis Function %if you select a RBF that supports it (Gausian, or 1st or 3rd order %polyharmonic spline), this also calculates a line integral between two %points.
上傳時間： 2021-07-02
上傳用戶：19800358905
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內部產生的數據，本實驗將彩條替換為 SD 內的 BMP 圖片數據，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
SH367309是5-16串鋰電池BMS用數字前端芯片，適用于總電壓不超過70V的鋰電池Pack。 SH367309工作在保護模式下，可獨立保護鋰電池Pack。提供過充電保護、過放電保護、溫度保護、充放電過流保護、短路保護、二次過充電保護等。集成平衡開關提高電芯一致性。 SH367309工作在采集模式下，可配合MCU管理鋰電池Pack，同時使能所有保護功能。 SH367309內置VADC，用于采集電芯電壓、溫度以及電流；內置CADC采集電流，用于統計Pack剩余容量；內置EEPROM，用于保存保護閾值及延時等可調參數；內置TWI通訊接口，用于操作相關寄存器及EEPROM。產品特性介紹■ 硬件保護功能 - 過充電保護功能 - 過放電保護功能 - 充放電高溫保護功能 - 充放電低溫保護功能 - 充放電過流保護功能 - 短路保護功能 - 二次過充電保護功能 - 斷線保護功能■ 內置平衡開關■ 禁止低壓電芯充電功能■ 小電流檢測功能■ 支持亂序上下電■ 內置看門狗模塊■ 模式設計 - 采集模式（SH367309配合MCU應用） - 保護模式（SH367309獨立應用） - 倉運模式 - 燒寫模式■ 13-bit VADC用于采集電壓/溫度/電流 - 轉換頻率：10Hz - 16路電壓采集通道 - 1路電流采集通道 - 3路溫度采集通道■ 16-bit ?-?CADC用于采集電流 - 轉換頻率：4Hz■ 內置EEPROM - 編程/擦除次數：≤ 100次■ 穩壓電源 - 3.3V（25mA@MAX）■ MOSFET驅動：電池組負端NMOS驅動■ CTL管腳：優先控制充放電MOSFET關閉■ TWI通訊接口：支持CRC8校驗■ 低功耗設計： - IDLE狀態 - SLEEP狀態 - Powerdown狀態■ 封裝 - TQFP48L
標簽： sh367309
上傳時間： 2021-11-22
上傳用戶：jason_vip1
FPGA讀取OV5640攝像頭數據并通過VGA或LCD屏顯示輸出的Verilog邏輯源碼Quartus工程文件+文檔說明，FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上傳時間： 2021-12-18
上傳用戶：
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數據寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
PW4203 is a 4.5-22V input, 2A multi-cell synchronous Buck Li-Ion battery charger, suitable forportable application. select pin is convenient for multi-cell charging. 800 kHz synchronous buckregulator integrates of 22V rating FETs with ultra low on- resistance to achieve high efficiency andsimple circuit design.The PW4203 is available in an 8-pin SOP package, provides a very compact system solution andgood thermal conductance
標簽： pw4203
上傳時間： 2022-02-11
上傳用戶：
數字示波器功能強大,使用方便,但是價格相對昂貴。本文以Ti的MSP430F5529為主控器,以Altera公司的EP2C5T144C8 FPGA器件為邏輯控制部件設計數字示波器。模擬信號經程控放大、整形電路后形成方波信號送至FPGA測頻,根據頻率值選擇采用片上及片外高速AD分段采樣。FPGA控制片外AD采樣并將數據輸入到FIFO模塊中緩存,由單片機進行頻譜分析。測試表明:簡易示波器可以實現自動選檔、多采樣率采樣、高精度測頻及頻譜分析等功能。Digital oscilloscope is powerful and easy to use, but also expensive. The research group designed a low-cost digital oscilloscope, the chip of MSP430F5529 of TI is chosen as the main controller and the device of EP2C5T144C8 of Altera company is used as the logic control unit. Analog signal enter the programmable amplifier circuit, shaping circuit and other pre-processing circuit. The shaped rectangular wave signal is sent to FPGA for measure the frequency. According to the frequency value to select AD on-chip or off-chip high-speed AD for sampling. FPGA controls the off-chip AD sampling and buffers AD data by FIFO module. The single chip microcomputer receives the data, and do FFT for spectrum analysis. The test shows that the simple oscilloscope can realize automatic gain selection, sampling at different sampling rates, high precision frequency measurement and spectrum analysis.
上傳時間： 2022-03-27
上傳用戶：
