Vishay新型功率MOSFET采用反向?qū)б齌O-252DPAK封裝
標(biāo)簽： Vishay MOSFET 252 DP
上傳時(shí)間： 2013-11-09
上傳用戶：immanuel2006
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時(shí)間： 2013-11-07
上傳用戶：swing
ADS to MDK 轉(zhuǎn)換例程由西安畢博制作的MDK指導(dǎo)視頻，下載后打開(kāi)Realview mdk1.htm頁(yè)面即可播放，內(nèi)容包括：模擬仿真、開(kāi)發(fā)環(huán)境的建立、啟動(dòng)代碼概述等，是您盡快上手MDK的好工具
標(biāo)簽： ADS MDK to 轉(zhuǎn)換
上傳時(shí)間： 2013-12-21
上傳用戶：dalidala
針對(duì)UHF讀寫器設(shè)計(jì)中，在符合EPC Gen2標(biāo)準(zhǔn)的情況下，對(duì)標(biāo)簽返回的高速數(shù)據(jù)進(jìn)行正確解碼以達(dá)到正確讀取標(biāo)簽的要求，提出了一種新的在ARM平臺(tái)下采用邊沿捕獲統(tǒng)計(jì)定時(shí)器數(shù)判斷數(shù)據(jù)的方法，并對(duì)FM0編碼進(jìn)行解碼。與傳統(tǒng)的使用定時(shí)器定時(shí)采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時(shí)器定時(shí)誤差累積的影響；可以將捕獲定時(shí)器數(shù)中斷與數(shù)據(jù)判斷解碼相對(duì)分隔開(kāi)，使得中斷對(duì)解碼影響很小，實(shí)現(xiàn)捕獲與解碼的同步。通過(guò)實(shí)驗(yàn)表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標(biāo)簽的時(shí)間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
標(biāo)簽： UHF FM0 讀寫器 解碼技術(shù)
上傳時(shí)間： 2013-11-10
上傳用戶：liufei
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時(shí)間： 2013-10-28
上傳用戶：15501536189
mm to mil tool,mm to mil tool_mm轉(zhuǎn)mil轉(zhuǎn)換工具
上傳時(shí)間： 2013-10-31
上傳用戶：515414293
mm to mil tool,mm to mil tool_mm轉(zhuǎn)mil轉(zhuǎn)換工具
上傳時(shí)間： 2013-11-14
上傳用戶：crazyer
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software algorithms by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時(shí)間： 2013-10-12
上傳用戶：kang1923
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：jyycc
波長(zhǎng)信號(hào)的解調(diào)是實(shí)現(xiàn)光纖光柵傳感網(wǎng)絡(luò)的關(guān)鍵，基于現(xiàn)有的光纖光柵傳感器解調(diào)方法，提出一種基于FPGA的雙匹配光纖光柵解調(diào)方法，此系統(tǒng)是一種高速率、高精度、低成本的解調(diào)系統(tǒng)，并且通過(guò)引入雙匹配光柵有效地克服了雙值問(wèn)題同時(shí)擴(kuò)大了檢測(cè)范圍。分析了光纖光柵的測(cè)溫原理并給出了該方案軟硬件設(shè)計(jì)，綜合考慮系統(tǒng)的解調(diào)精度和FPGA的處理速度給出了基于拉格朗日的曲線擬合算法。 Abstract: Sensor is one of the most important application of the fiber grating. Wavelength signal demodulating is the key techniques to carry out fiber grating sensing network， based on several existing methods of fiber grating sensor demodulation inadequate， a two-match fiber grating demodulation method was presented. This system is a high-speed， high precision， low-cost demodulation system. And by introducing a two-match grating effectively overcomes the problem of double value while expands the scope of testing. This paper analyzes the principle of fiber Bragg grating temperature and gives the software and hardware design of the program. Considering the system of demodulation accuracy and processing speed of FPGA，this paper gives the curve fitting algorithm based on Lagrange.
標(biāo)簽： FPGA 光纖光柵 解調(diào)系統(tǒng)
上傳時(shí)間： 2013-10-10
上傳用戶：zxc23456789
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