A spatiotemporal chaotic map is digitized to develop a highly paralleled PRBS generator that accommodates to FPGA (Field Programmable Gate Array) implementation in present paper.
數(shù)字示波器功能強(qiáng)大,使用方便,但是價(jià)格相對(duì)昂貴。本文以Ti的MSP430F5529為主控器,以Altera公司的EP2C5T144C8 FPGA器件為邏輯控制部件設(shè)計(jì)數(shù)字示波器。模擬信號(hào)經(jīng)程控放大、整形電路后形成方波信號(hào)送至FPGA測(cè)頻,根據(jù)頻率值選擇采用片上及片外高速AD分段采樣。FPGA控制片外AD采樣并將數(shù)據(jù)輸入到FIFO模塊中緩存,由單片機(jī)進(jìn)行頻譜分析。測(cè)試表明:簡(jiǎn)易示波器可以實(shí)現(xiàn)自動(dòng)選檔、多采樣率采樣、高精度測(cè)頻及頻譜分析等功能。Digital oscilloscope is powerful and easy to use, but also expensive. The research group designed a low-cost digital oscilloscope, the chip of MSP430F5529 of TI is chosen as the main controller and the device of EP2C5T144C8 of Altera company is used as the logic control unit. Analog signal enter the programmable amplifier circuit, shaping circuit and other pre-processing circuit. The shaped rectangular wave signal is sent to FPGA for measure the frequency. According to the frequency value to select AD on-chip or off-chip high-speed AD for sampling. FPGA controls the off-chip AD sampling and buffers AD data by FIFO module. The single chip microcomputer receives the data, and do FFT for spectrum analysis. The test shows that the simple oscilloscope can realize automatic gain selection, sampling at different sampling rates, high precision frequency measurement and spectrum analysis.
關(guān)于FPGA流水線設(shè)計(jì)的論文\r\nThis work investigates the use of very deep pipelines for\r\nimplementing circuits in FPGAs, where each pipeline\r\nstage is limited to a single FPGA logic element (LE). The\r\narchitecture and VHDL design of a parameterized integer\r\na
針對(duì)使用硬件描述語(yǔ)言進(jìn)行設(shè)計(jì)存在的問題，提出一種基于FPGA并采用DSP Builder作為設(shè)計(jì)工具的數(shù)字信號(hào)處理器設(shè)計(jì)方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設(shè)計(jì)流程，設(shè)計(jì)了一個(gè)12階FIR 低通數(shù)字濾波器，通過Quartus 時(shí)序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測(cè)試對(duì)設(shè)計(jì)進(jìn)行了驗(yàn)證。結(jié)果表明，所設(shè)計(jì)的FIR 濾波器功能正確，性能良好。
Abstract:
Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
