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為提高電容測量精度，針對電容式傳感器的工作原理設計了基于PIC16LF874單片機電容測量模塊。簡單闡述了電容測量電路的應用背景和國內外研究現狀，介紹了美國Microchip公司PIC16LF874單片機的特性。電容式傳感器輸出的動態微弱電容信號通過PS021型電容數字轉換器把模擬量數據轉換成數字量數據，所測數據由PIC16LF874單片機應用程序進行處理、顯示和保存。實驗結果表明，固定電容標稱值為10~20 pF 的測量值相對誤差在1%以內，同時也可知被測電容容值越大，測量值和標稱值相對誤差越小。
Abstract:
To improve the accuracy of capacitance measurement，aimed at the principle of work of mercury capacitance acceleration transducer，the design of micro capacitance measurement circuit is based on the key PIC16LF874 chip. Briefly discusses the application of the capacitance measuring circuit for the background and status of foreign researchers，focusing on the United States PIC16LF874 microcontroller features. Capacitive sensor outputed signal through the dynamics of weak PS021-chip capacitors （capacitancedigital converter） to convert analog data into digital data，the measured data from the PIC16LF874 microcontroller application process， display and preservation. Experimental results show that the fixed capacitor 10pF ~ 20pF nominal value of the measured value of relative error is within 1%，but also it canbe seen the value of the measured capacitance larger，measuring value and the nominal value of relative error smaller.
標簽：
PIC
874
16
LF
上傳時間：
2013-10-29
上傳用戶：wojiaohs
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The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power switches, sensors,
push buttons, LEDs, fans, etc.
標簽：
SMBus
9534
PCA
I2C
上傳時間：
2013-11-17
上傳用戶：vodssv
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The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel
Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to
enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements
include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O
configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a
simple solution when additional I/O is needed for ACPI power switches, sensors,
push buttons, LEDs, fans, etc.
標簽：
interru
SMBus
power
9534
上傳時間：
2013-10-10
上傳用戶：inwins
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The PCA9535 and PCA9535C are 24-pin CMOS devices that provide 16 bits of GeneralPurpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and wasdeveloped to enhance the NXP Semiconductors family of I2C-bus I/O expanders. Theimprovements include higher drive capability, 5 V I/O tolerance, lower supply current,individual I/O configuration, and smaller packaging. I/O expanders provide a simplesolution when additional I/O is needed for ACPI power switches, sensors, push buttons,LEDs, fans, etc.
標簽：
9535
PCA
9535C
I2C
上傳時間：
2013-10-21
上傳用戶：愛死愛死
-
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
標簽：
C-bus
9555
SMBu
PCA
上傳時間：
2013-11-13
上傳用戶：fredguo
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基于PIC單片機的低功耗讀卡器硬件設計:本文提出了一個完整的基于串口的智能讀卡器子系統設計方案并將其實現。讀卡器的設計突出了小型化的要求，全部器件使用貼片封裝。為了減小讀卡器的體積，設計中還使用了串口竊電的技術，使用串口信號線直接給讀卡器供電。為此，讀卡器使用了省電的設計，采用了省電的集成電路，并大膽簡化了許多傳統的設計電路。關鍵字： 讀卡器， 單片機， 串口竊電
Abstract： This paper aims to put forward a complete design of Smart IC card reader based onSerial Port and propose the way of realizing it for the purpose of Network Security. SMD isadopted to make Smart IC reader smaller in this design. To reduce the volume of Smart ICreader， Serial Port powered technology is employed to get power from the signal line of Serial Port. For this reason， low-power consumption components are adopted in the design and some traditional designs are simplified to reduce the power consumption.Keywords： Card Reader； Single-chip Computer； Serial Port Powered
IC 卡系統保存了加密算法所需要的工作密鑰，供加密算法對網絡上傳輸的數據加密使用，是整個系統網絡安全的核心。在IC 卡子系統中，讀卡器是一個重要的部分。它起著管理IC卡、在IC 卡和PC或網絡計算機間傳遞數據的重要作用。本文以一片PIC單片機為核心完成了基于RS232 串口的讀卡器的硬件設計。
標簽：
PIC
單片機
低功耗
讀卡器
上傳時間：
2014-04-14
上傳用戶：wanghui2438
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構
上傳時間：
2013-11-13
上傳用戶：瓦力瓦力hong
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽：
UltraScale
Xilinx
架構
上傳時間：
2013-11-21
上傳用戶：wxqman
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This version of the code is compatible only with the AT89C2051 due to the
location of the data buffer and stack in RAM. The code may be modified to
work with the AT89C1051 by relocating or resizing the buffer and stack to
fit into the smaller amount of RAM available in the AT89C1051.
標簽：
the
compatible
location
version
上傳時間：
2015-04-05
上傳用戶：changeboy
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This document describes the uIP TCP/IP stack. The uIP TCP/IP stack is an extremely small implementation of the TCP/IP protocol suite intended for embedded systems running low-end 8 or 16-bit microcon-trollers. The code size and RAM requirements of uIP is an order of magnitude smaller than other generic TCP/IP stacks today.
標簽：
stack
implementat
TCP
describes
上傳時間：
2015-09-18
上傳用戶：zsjinju
