The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
AXI Bus Functional Model v1.1 Product Brief.pdf
上傳時間： 2015-01-01
上傳用戶：kbnswdifs
Express Mode uses an 8-bit wide bus path for fast configuration of Xilinx FPGAs. Thisapplication note provides information on how to perform Express configuration specifically forthe Spartan™-XL family. The Express mode signals and their associated timing are defined.The steps of Express configuration are described in detail, followed by detailed instructions thatshow how to implement the configuration circui
標簽： Spartan-XL Express XAPP FPGA
上傳時間： 2015-01-02
上傳用戶：nanxia
The PLB BRAM Interface Controller is a module thatattaches to the PLB (Processor Local Bus).
上傳時間： 2013-10-27
上傳用戶：Breathe0125
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
隨著串行通訊進入更多應用領域，因此，在一些應用里，需要對通訊功能的報文識別位提出分配標準化的要求。原先的地址范圍由 11 個識別位定義，如果地址范圍擴大，則這些應用就可以更好地由 CAN 來實現。因此引入了第二種報文格式（‘擴展格式’）的概念，其定義的地址范圍更寬，由 29 位定義。
上傳時間： 2013-11-10
上傳用戶：maqianfeng
The high defi nition multimedia interface (HDMI) is fastbecoming the de facto standard for passing digitalaudio and video data in home entertainment systems.This standard includes an I2C type bus called a displaydata channel (DDC) that is used to pass extended digitalinterface data (EDID) from the sinkdevice (such as adigital TV) to the source device (such as a digital A/Vreceiver). EDID includes vital information on the digitaldata formats that the sink device can accept. The HDMIspecifi cation requires that devices have less than 50pFof input capacitance on their DDC bus lines, which canbe very diffi cult to meet. The LTC®4300A’s capacitancebuffering feature allows devices to pass the HDMI DDCinput capacitance compliance test with ease.
上傳時間： 2013-11-21
上傳用戶：tian126vip
ACNET-600/622為工業級產品，可以工作在-25℃～+75℃的溫度范圍內。它具有10M/100M自適應以太網接口，CAN口通信最高波特率為1Mbps，完善的支持TCP Server、TCP Client和UDP等多種工作模式，每個CAN口可支持2個TCP連接或多達2×254個UDP“連接”，通過配置軟件用戶可以靈活的設定相關配置參數。
上傳時間： 2013-10-25
上傳用戶：竺羽翎2222
IEEE1394Diag is a GUI application that presents a graphical view of an IEEE1394 network and provides the ability to perform common 1394 operations such as async reads, writes, isoc listens and talks, as well as configuration rom browsing of all nodes present on a bus.
標簽： IEEE 1394 application graphical
上傳時間： 2015-04-02
上傳用戶：familiarsmile
